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  First Stage boot loader
Posted by: Chris66 - 01-04-2018, 11:28 AM - Forum: Linux on Rock64 - Replies (1)

Any chances of this will becoming Open source ?


  Where is "carl9170.ko"
Posted by: pine3228 - 01-04-2018, 03:35 AM - Forum: General Discussion on ROCK64 - Replies (2)

「carl9170.ko」は、「xenial-minimal-rock64-0.5.15-136-arm64.img.xz」のどこにあるのですか?
もしくは、どうすれば、ビルドできるのでしょうか?
Google Translate : 
Where are "carl9170.ko" and "carl9170.fw" in "xenial-minimal-rock64-0.5.15-136-arm64.img.xz"?
Or, how can I build it?


  Coupon codes
Posted by: WhiskerBiscuit - 01-03-2018, 08:12 PM - Forum: General Discussion on Pinebook - Replies (1)

I’m about to order my third SBC from Pine64, but at this point I really think as a repeat customer I should be able to get some sort of discount — even if it is free shipping.  So how about it?  Can I get the hoookup?  I’m not going to place an order without one.


  Archive of past Rock64 Linux Images?
Posted by: wbecks - 01-03-2018, 12:25 PM - Forum: General Discussion on ROCK64 - Replies (3)

Is there an archive of past community Rock64 Linux images?   Current releases of Ayufan seem to have incomplete audio support with no apparent way to direct audio output from the internal 3.5 mm headphone (A/V) jack.   There was a community SD card Linux image that I don't believe was Ayufan, that did support audio from the headphone jack dating back to the late October or November 2017 time frame.

Current Ayufan images do produce HDMI audio but nothing from the 3.5 mm A/V (headphone) jack.   I would appreciate any help with gaining access to back archives or help to configure audio on the headphone jack.

Thank you,

Bill, WA8WG


  40 pin header
Posted by: GaryLa - 01-03-2018, 11:15 AM - Forum: General Discussion on ROCK64 - Replies (5)

Hello,

I assume this is up-to-date: ROCK64_Schematic_v2.0_20170704.pdf

Is it true that the following "dedicated signals" could be re-purposed as regular IO as they only go the 40-pin header?

CLK32KOUT_M1
UART2_TX
UART2_RX


Also, why does SPI_CSN0_M2 appear on this header? It is dedicated as a chip select on SPI flash IC U1 (the GD25Q128CS).

Any use of this pin as either SPI or GPIO will cause U1 to drive the MISO pin (pin 21 on the 40 pin header).

Also, the graphic that shows the 40-pin header (ROCK64_Pi-2 _and_Pi_P5+_Bus.pdf) states the the SDMMC0_xxxx pins can be used as GPIO as long as no MicroSD is used.

How do these pins operate during boot? If they are intended to be used as GPIO by an application, the boot process may inadvertently cause a daughterboard to react because the application hasn't booted yet.

Any guidance would be appreciated.


  Compile kernel /Android and can't detect SDHC from Kernel
Posted by: spbrain - 01-03-2018, 12:55 AM - Forum: Android on PINE A64-LTS / SOPINE - Replies (6)

Hello?

I found how to compile compile pine64 android 5.1.1 from https://gitlab.com/pine64-android/manifest/wikis/home.

I modified some parameters (LPDDR3 define from uboot) and I made sun50iw1p1_android_Baomi-db1000_uart0.img and write to sdcard using Phoenix program(Start Up Option).

Then finally confirmed the boot screen.

But Strangely, system.img was not mounted.

console output is

  30.041548] fs_mgr: __mount(source=/dev/block/by-name/system,target=/system,type=ext4)=-1
[   30.050642] fs_mgr: Failed to mount an un-encryptable or wiped partition on/dev/block/by-name/system at /system options: (null) error: No such file or directory
[   49.727478] fs_mgr: check_fs(): mount(/dev/block/by-name/cache,/cache,ext4)=-1
[   49.735547] fs_mgr: begin to format ext4 buffer : /dev/block/mmcblk0p10[   49.743178] fs_mgr: Not running /system/bin/e2fsck on /dev/block/by-name/cache (executable not in system


And Kernel Parameters
[    0.000000] Kernel command line: enforcing=1 earlyprintk=sunxi-uart,0x01c28000 initcall_debug=0 console=ttyS0,115200 loglevel=8 root=/dev/mmcblk0p7 init=/init partitions=bootloader@mmcblk0p2:env@mmcblk0p5:boot@mmcblk0p6Confusedystem@mmcblk0p7:misc@mmcblk0p8:recovery@mmcblk0p9:cache@mmcblk0p10:metadata@mmcblk0p11:private@mmcblk0p12:alog@mmcblk0p13:UDISK@mmcblk0p1 cma=384M androidboot.selinux=permissive androidboot.serialno=74005034440c080b038e androidboot.hardware=sun50iw1p1

And I found problem log from kernel message.
As Image from offical site "http://files.pine64.org/os/SOPINE/android/android-ver5.1.1-20160630-sopine-8GB.img.gz", 
Linux Kernel found "mmcblk0".
Log is 
==========================================
9.929729] mmc0: new high speed SDHC card at address 59b4
9.930831] mmcblk0: mmc0:59b4 USD00 29.5 GiB
==========================================
But compiled linux kernel can not found SDHC card.

I tried 8GB SDHC Card but it same.
What do I modify bootloader config or kernel ??
How do I fix this problem?

SD Card Init Log is below from kernel and no detect SDHC card 
=======================================
[    8.730445] sunxi-mmc 1c0f000.sdmmc: SD/MMC/SDIO Host Controller Driver(v0.20 2015-7-13 16:28) Compiled in Jan  3 2018 at 09:36:58
[    8.743342] sunxi-mmc 1c0f000.sdmmc: regulator prop vmmc,str none
[    8.750009] sunxi-mmc 1c0f000.sdmmc: regulator prop vqmmc,str none
[    8.756760] sunxi-mmc 1c0f000.sdmmc: regulator prop vdmmc,str vcc-sdc
[    8.763920] sunxi-mmc 1c0f000.sdmmc: No vmmc regulator found
[    8.770110] sunxi-mmc 1c0f000.sdmmc: No vqmmc regulator found
[    8.776929] sunxi-mmc 1c0f000.sdmmc: Got CD GPIO #166.
[    8.782910] sunxi-mmc 1c0f000.sdmmc: sdc set ios: clk 0Hz bm PP pm UP vdd 21 width 1 timing LEGACY(SDR12) dt B
[    8.793861] sunxi-mmc 1c0f000.sdmmc: no vqmmc,Check if there is regulator
[    8.816982] sunxi-mmc 1c0f000.sdmmc: sdc set ios: clk 400000Hz bm PP pm ON vdd 21 width 1 timing LEGACY(SDR12) dt B
[    8.846524] sunxi-mmc 1c0f000.sdmmc: base:0xffffff80000ba000 irq:92
[    8.853803] sunxi-mmc 1c10000.sdmmc: SD/MMC/SDIO Host Controller Driver(v0.20 2015-7-13 16:28) Compiled in Jan  3 2018 at 09:36:58
[    8.866672] sunxi-mmc 1c10000.sdmmc: Can't get vmmc regulator string
[    8.873611] sunxi-mmc 1c10000.sdmmc: Can't get vqmmc regulator string
[    8.880656] sunxi-mmc 1c10000.sdmmc: Can't get vdmmc regulator string
[    8.887695] get() with no identifier
[    8.891594] get() with no identifier
[    8.895491] get() with no identifier


  ROCK64 does not recognize USB Wifi module (WL300NU-G)
Posted by: pine3228 - 01-02-2018, 10:12 PM - Forum: General Discussion on ROCK64 - Replies (2)

私は、WL300NU-GというWifiデバイスをROCK64に接続しました。
しかし、ifconfigを見てもデバイスが表示されませんでした。
どうすればよいのですか?
ちなみに、使用イメージは、
xenial-minimal-rock64-0.5.15-136-arm64.img.xz
です。

Google Translate : 
I connected a Wifi device called WL 300 NU - G to ROCK 64.
However, when you look at ifconfig, the device was not displayed.
What should I do?
By the way,
xenial-minimal-rock64-0.5.15-136-arm64.img.xz


  SPI Interface questions
Posted by: bencrosby - 01-02-2018, 05:40 PM - Forum: Rock64 Hardware and Accessories - Replies (9)

Hi folks,

I'm somewhat confused by the SPI interfaces in the RK3328 and thus their application in the ROCK64.

I've dug through all the documentation. It appears that there are three SPI interfaces in the RK3328, per Pg. 483 of the technical reference manual.

Code:
INTERFACE    CLOCK    RXD    TXD    CSN0    CSN1
                    
SPI0 (m0)    clkm0 : GPIO2B0    rxdm0 : GPIO2B2    txdm0 : GPIO2B1    csn0m0 : GPIO2B3    csn1m0 : GPIO2B4
SPI1 (m1)    clkm1 : GPIO3C7    rxdm1 : GPIO3D0    txdm1 : GPIO3D1    csn0m1 : GPIO3D2    csn1m1 : GPIO3D3
SPI2 (m2)    clkm2 : GPIO3A0    rxdm2 : GPIO3A2    txdm2 : GPIO3A1    csn0m2 : GPIO3B0    N/A


In ROCK64_Schematic_v2.0_20171019.pdf and the ROCK64 Pi2 Bus diagram....

Pi2 Bus Pin 24 is marked as "SPI_CSN0_M2", Pin 26 is marked as "SPI_CSN1_M0"

This is the first thing that confused me. Why do we have only one CS belonging to two different SPI interfaces on the header ?

The SPI2 (m2) Interface is exposed on the header. It has only on CS, and can only have one device on the bus. 
It appears that bus m2 is the same one used for the ROCK64 on-board 128M flash chip (U1) per page 6 of the schematics. 

Question 1: If so, how does one use the SPI interface on the Pi-2 bus without also addressing the onboard 128M Flash ?

Question 2: What was the purpose of exposing SPI_CSN1_M0 to the header when the rest of SPI_M0 is inaccessible ?

As far as I can tell, interface M0 and M1 are not used. In fact, it may even be that these interfaces aren't available on the BGA - I can't find them on the Ball Map.

I am wondering if future versions of the ROCK64 will make any changes? If so, is there a forum or suitable place to send suggestions ?

Suggestion: If possible, populate the header with a usable SPI bus e.g. m0 or m1, and provide both cs lines, e.g.

Pin 19: SPI_TXD_Mx 
Pin 21: SPI_RXD_Mx
Pin 23: SPI_CLK_Mx
Pin 24: SPI_CSN0_Mx
Pin 26: SPI_CSN1_Mx

Cheers.


  pi case conversions for rock64
Posted by: sandradabo00 - 01-01-2018, 12:34 PM - Forum: Rock64 Hardware and Accessories - Replies (8)

Hello all,
I am looking for a case for rock64 board that is available in Europe. There does not seem to be any.
Has anyone managed to adapt an existing raspberry pi case for rock64 ? I would like to make a media center so it should be good looking (and cheap).
Any guides out there ?

Thanks


  Faster CPU speed than 1.3GHZ?
Posted by: RamenNoodles - 12-31-2017, 08:11 PM - Forum: Linux on Rock64 - Replies (2)

Hello. Is it possible in any way to increase the clock speed on the CPU if I add one of those little heatsink things to it? I'm expecting no but just wanna be sure