04-08-2019, 02:54 PM
How are you planning on controlling the GPIO Devices ? Via the legacy /sys/class/gpio driver ?
I am currently trying to write a GPIO kernel driver to the new standard. There are a lot of anomalies in the documentation but I am composing a complete spreadsheet of the PMU/GRF Registers if thats how you where planning on doing it ?
I am almost finished.
There are 5 GPIO Banks supporting a total of 122 GPIO's only a few of which can be accessed by user space;
They all have PAD designation A,B,C,D each with its own IOMUX Register
gpio0 Allocated to PMU Registers as can be used for wake-up.
gpio1 Allocated to PMU Registers as can be used for wake-up.
gpio2 GRF Registers and used for SPI/12C/PMW etc as well as exposed GPIO
gpio3 GRF Registers and used for SPI/12C/PMW etc as well as exposed GPIO
gpio4 GRF Registers and used for SPI/12C/PMW etc as well as exposed GPIO
I am currently trying to write a GPIO kernel driver to the new standard. There are a lot of anomalies in the documentation but I am composing a complete spreadsheet of the PMU/GRF Registers if thats how you where planning on doing it ?
I am almost finished.
There are 5 GPIO Banks supporting a total of 122 GPIO's only a few of which can be accessed by user space;
They all have PAD designation A,B,C,D each with its own IOMUX Register
gpio0 Allocated to PMU Registers as can be used for wake-up.
gpio1 Allocated to PMU Registers as can be used for wake-up.
gpio2 GRF Registers and used for SPI/12C/PMW etc as well as exposed GPIO
gpio3 GRF Registers and used for SPI/12C/PMW etc as well as exposed GPIO
gpio4 GRF Registers and used for SPI/12C/PMW etc as well as exposed GPIO