JTAG/SWD on Quartz64 model A
#4
Here is an article I wrote about how I got it working: http://notes.zahoryzontnik.com

There are significant differences from the process described by Chris, but reading his article put me on the right track. Specifically the register addresses and values are different. One needs an openocd config file for RK3566 that I had to create (it can be copied from the article - once I've tested it more I'll submit it as a contribution to openocd) . It was created based on scanning the rom table. And one needs to disable sleep/idle states for the cores. This is also described there.

The two pins labelled ARM_JTAG are indeed JTAG and SWD. There is a procedure to switch them between JTAG and SWD. OpenOCD runs that procedure automatically when SWD as protocol is specified.

In general debugging via SWD works fine. Hardware breakpoints and watch points work, single stepping through the kernel (including irq handlers) works, memory copy works. Mind I've used jlink hardware only as my debug probe and instead of "break" use "hbreak" when kernel debugging.
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Messages In This Thread
JTAG/SWD on Quartz64 model A - by capablegh - 07-30-2021, 02:33 PM
RE: JTAG/SWD on Quartz64 model A - by capablegh - 08-04-2021, 06:05 AM
RE: JTAG/SWD on Quartz64 model A - by capablegh - 08-12-2021, 02:29 PM
RE: JTAG/SWD on Quartz64 model A - by Randomuser - 08-15-2022, 06:19 PM
RE: JTAG/SWD on Quartz64 model A - by fatalfeel - 10-03-2022, 03:16 PM

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