JTAG/SWD on Quartz64 model A - Printable Version +- PINE64 (https://forum.pine64.org) +-- Forum: Quartz64 (https://forum.pine64.org/forumdisplay.php?fid=166) +--- Forum: General Discussion on Quartz64 (https://forum.pine64.org/forumdisplay.php?fid=167) +--- Thread: JTAG/SWD on Quartz64 model A (/showthread.php?tid=14554) |
JTAG/SWD on Quartz64 model A - capablegh - 07-30-2021 Hello. The Quartz64 model A I purchased should be here in a few days. I would like to connect a JTAG/SWD debugger to it. Where could I find documentation where this is described? In the schematics for the board, I see mention of JTAG in few places, but I am not sure where physically the pins are on the board. Can anyone provide specifics? Also, aside from the RK3566 datasheet are there any reference manuals/guides for the board? Where can I find these? Also, the same for the Quartz64. RE: JTAG/SWD on Quartz64 model A - capablegh - 08-04-2021 (07-30-2021, 02:33 PM)capablegh Wrote: Hello. No response from Pine64? I understand the board is not ready for production use, and I am using it only for exploring/experimenting. Surely, a JTAG is present that was used for the UBoot and Linux porting efforts. RE: JTAG/SWD on Quartz64 model A - capablegh - 08-12-2021 (08-04-2021, 06:05 AM)capablegh Wrote:(07-30-2021, 02:33 PM)capablegh Wrote: Hello. An article https://crwulff.blogspot.com/p/rock64.html I came across by a Chris Wulff (thank you Chris), is about JTAG/SWD on Rock64. Apparently the what appear to be two JTAG pins (TCK and TMS), seem to really be SWD pins (SWCLK and SWDIO). Similarly on the Quartz64 schematic I see ARM_JTAG_TCK and ARM_JTAG_SWD. Is it true that Quartz64 follows the same as for the Rock64? After all Quartz64 is after Rock64/RockPro64. Could anyone please confirm that indeed the ARM_JTAG labelled pins are actually SWD and not JTAG, and Chris Wulff's article/blog is applicable to Quartz64? RE: JTAG/SWD on Quartz64 model A - Randomuser - 08-15-2022 Here is an article I wrote about how I got it working: http://notes.zahoryzontnik.com There are significant differences from the process described by Chris, but reading his article put me on the right track. Specifically the register addresses and values are different. One needs an openocd config file for RK3566 that I had to create (it can be copied from the article - once I've tested it more I'll submit it as a contribution to openocd) . It was created based on scanning the rom table. And one needs to disable sleep/idle states for the cores. This is also described there. The two pins labelled ARM_JTAG are indeed JTAG and SWD. There is a procedure to switch them between JTAG and SWD. OpenOCD runs that procedure automatically when SWD as protocol is specified. In general debugging via SWD works fine. Hardware breakpoints and watch points work, single stepping through the kernel (including irq handlers) works, memory copy works. Mind I've used jlink hardware only as my debug probe and instead of "break" use "hbreak" when kernel debugging. RE: JTAG/SWD on Quartz64 model A - fatalfeel - 10-03-2022 plz refer to this https://t.rock-chips.com/forum.php?mod=viewthread&tid=4112&extra=page%3D1 |