06-23-2020, 01:38 PM (This post was last modified: 06-23-2020, 02:04 PM by Syonyk.)
Sorry for what I hope is a stupid question...
I'm running a Pinebook Pro with the "mrfixit BSP uboot" - for deep sleep and such.
I'm using the Manjaro/tsys 5.7 kernel with hwaccel patches.
Uboot log:
Spoiler:
Code:
DDR Version 1.20 20190314
In
channel 0
CS = 0
MR0=0x98
MR4=0x1
MR5=0xFF
MR8=0x8
MR12=0x72
MR14=0x72
MR18=0x0
MR19=0x0
MR24=0x8
MR25=0x0
CS = 1
MR0=0x18
MR4=0x1
MR5=0xFF
MR8=0x8
MR12=0x72
MR14=0x72
MR18=0x0
MR19=0x0
MR24=0x8
MR25=0x0
channel 1
CS = 0
MR0=0x98
MR4=0x1
MR5=0xFF
MR8=0x8
MR12=0x72
MR14=0x72
MR18=0x0
MR19=0x0
MR24=0x8
MR25=0x0
CS = 1
MR0=0x18
MR4=0x1
MR5=0xFF
MR8=0x8
MR12=0x72
MR14=0x72
MR18=0x0
MR19=0x0
MR24=0x8
MR25=0x0
channel 0 training pass!
channel 1 training pass!
change freq to 400MHz 0,1
channel 0
CS = 0
MR0=0x98
MR4=0x1
MR5=0xFF
MR8=0x8
MR12=0x72
MR14=0x72
MR18=0x0
MR19=0x0
MR24=0x8
MR25=0x0
CS = 1
MR0=0x18
MR4=0x1
MR5=0xFF
MR8=0x8
MR12=0x72
MR14=0x72
MR18=0x0
MR19=0x0
MR24=0x8
MR25=0x0
channel 1
CS = 0
MR0=0x98
MR4=0x1
MR5=0xFF
MR8=0x8
MR12=0x72
MR14=0x72
MR18=0x0
MR19=0x0
MR24=0x8
MR25=0x0
CS = 1
MR0=0x18
MR4=0x1
MR5=0xFF
MR8=0x8
MR12=0x72
MR14=0x72
MR18=0x0
MR19=0x0
MR24=0x8
MR25=0x0
channel 0 training pass!
channel 1 training pass!
change freq to 800MHz 1,0
Channel 0: LPDDR4,800MHz
Bus Width=32 Col=10 Bank=8 Row=15/15 CS=2 Die Bus-Width=16 Size=2048MB
Channel 1: LPDDR4,800MHz
Bus Width=32 Col=10 Bank=8 Row=15/15 CS=2 Die Bus-Width=16 Size=2048MB
256B stride
ch 0 ddrconfig = 0x101, ddrsize = 0x2020
ch 1 ddrconfig = 0x101, ddrsize = 0x2020
pmugrf_os_reg[2] = 0x3AA1FAA1, stride = 0xD
OUT
Boot1: 2019-03-14, version: 1.19
CPUId = 0x0
ChipType = 0x10, 249
SdmmcInit=2 0
BootCapSize=100000
UserCapSize=59640MB
FwPartOffset=2000 , 100000
mmc0:cmd8,20
mmc0:cmd5,20
mmc0:cmd55,20
mmc0:cmd1,20
mmc0:cmd8,20
mmc0:cmd5,20
mmc0:cmd55,20
mmc0:cmd1,20
mmc0:cmd8,20
mmc0:cmd5,20
mmc0:cmd55,20
mmc0:cmd1,20
SdmmcInit=0 1
StorageInit ok = 70518
SecureMode = 0
SecureInit read PBA: 0x4
SecureInit read PBA: 0x404
SecureInit read PBA: 0x804
SecureInit read PBA: 0xc04
SecureInit read PBA: 0x1004
SecureInit read PBA: 0x1404
SecureInit read PBA: 0x1804
SecureInit read PBA: 0x1c04
SecureInit ret = 0, SecureMode = 0
atags_set_bootdev: ret:(0)
GPT part: 0, name: loader1, start:0x40, size:0x1fc0
GPT part: 1, name: boot_efi, start:0x2000, size:0x6000
GPT part: 2, name: linux_boot, start:0x8000, size:0x78000
GPT part: 3, name: linux_root, start:0x80000, size:0x73fbfdf
no find partition:uboot.
LoadTrust Addr:0x4000
No find bl30.bin
No find bl32.bin
Load uboot, ReadLba = 2000
Load OK, addr=0x200000, size=0xdd03c
RunBL31 0x10000
NOTICE: BL31: v1.3(debug):22b599a
NOTICE: BL31: Built : 11:03:32, Jul 10 2019
NOTICE: BL31: Rockchip release version: v1.1
INFO: GICv3 with legacy support detected. ARM GICV3 driver initialized in EL3
INFO: Using opteed sec cpu_context!
INFO: boot cpu mask: 0
INFO: plat_rockchip_pmu_init(1181): pd status 3e
INFO: BL31: Initializing runtime services
WARNING: No OPTEE provided by BL2 boot loader, Booting device without OPTEE initialization. SMC`s destined for OPTEE will return SMC_UNK
ERROR: Error initializing runtime service opteed_fast
INFO: BL31: Preparing for EL3 exit to normal world
INFO: Entry point address = 0x200000
INFO: SPSR = 0x3c9
fdtdec_get_addr_size_fixed: reg: addr=ff770000, size=10000
fdtdec_get_addr_size_fixed: reg: addr=ff320000, size=1000
U-Boot 2017.09-03642-g183e247 (Nov 21 2019 - 20:31:11 -0500)
Model: Pine64 RK3399 Pinebook Pro
PreSerial: 2
DRAM: 3.9 GiB
Sysmem: init
Relocation Offset is: f5bf0000
I2c0 speed: 400000Hz
PMIC: RK808
vdd_center 900000 uV
vdd_log init 900000 uV
rk_board_init PWM2 pinctrl init fail!
rk_board_init: vcc3v0_sdio cannot set regulator value -38
vdd_center 900000 uV
DCDC_REG1@ vdd_center: 750000uV <-> 1400000uV, set 900000uV, enabling | suspend -61uV, disabled
DCDC_REG4@ vcc_1v8: 1800000uV <-> 1800000uV, set 1800000uV, enabling | suspend 1800000uV, enabling
LDO_REG1@ vcc1v8_dvp: 1800000uV <-> 1800000uV, set 1800000uV, enabling | suspend 1800000uV, enabling
LDO_REG4@ vcc_sd: 3300000uV <-> 3300000uV, set 3300000uV, enabling | suspend 3300000uV, enabling
LDO_REG7@ vcca1v8_codec: 1800000uV <-> 1800000uV, set 1800000uV, enabling | suspend 1800000uV, enabling
LDO_REG8@ vcc_3v0: 3000000uV <-> 3000000uV, set 3000000uV, enabling | suspend 3000000uV, enabling
SWITCH_REG2@ vcc3v3_s0: -61uV <-> -61uV, set 0uV, enabling | suspend -61uV, disabled
dc-12v@ dc_12v: 12000000uV <-> 12000000uV, set 12000000uV, enabling | suspend -61uV, enabling (ret: -38)
vcc-sys@ vcc_sys: 5000000uV <-> 5000000uV, set 5000000uV, enabling | suspend -61uV, enabling (ret: -38)
vcc3v3-sys@ vcc3v3_sys: 3300000uV <-> 3300000uV, set 3300000uV, enabling | suspend -61uV, enabling (ret: -38)
vcc-phy-regulator@ vcc_phy: -61uV <-> -61uV, set -61uV, enabling | suspend -61uV, enabling
led-regulator@ led_regulator: -61uV <-> -61uV, set -61uV, enabling | suspend -61uV, enabling
vcc5v0-host-en@ vcc5v0_host: 5000000uV <-> 5000000uV, set 5000000uV, enabling | suspend -61uV, enabling (ret: -38)
vcc5v0-usb3-host-regulator@vcc5v0_usb3_host: -61uV <-> -61uV, set -61uV, enabling | suspend -61uV, enabling
vcc5v0-typec0-en@ vcc5v0_typec0: -61uV <-> -61uV, set -61uV, enabling | suspend -61uV, enabling
vcc1v8-sdio@ vcc1v8_sdio: 1800000uV <-> 1800000uV, set 1800000uV, enabling | suspend -61uV, enabling (ret: -38)
vcc3v0-sdio@ vcc3v0_sdio: 3000000uV <-> 3000000uV, set 3000000uV, enabling | suspend -61uV, enabling ; init 3000000uV (ret: -38)
vdd_log init 900000 uV
vdd_log@ vdd_log: 800000uV <-> 1400000uV, set 900000uV, enabling | suspend -61uV, enabling ; init 900000uV
MMC: dwmmc@fe310000: 2, sdhci@fe330000: 0, dwmmc@fe320000: 1
Invalid bus 0 (err=-19)
*** Warning - spi_flash_probe_bus_cs() failed, using default environment
In: serial
Out: serial
Err: serial
Model: Pine64 RK3399 Pinebook Pro
Bootdev(atags): mmc 0
PartType: EFI
rockchip_get_boot_mode: Could not found misc partition
boot mode: None
init_resource_list: failed to get resource part, ret=-1
Can't find file:logo.bmp
failed to display uboot logo
CLK: (uboot. arml: enter 816000 KHz, init 816000 KHz, kernel 0N/A)
CLK: (uboot. armb: enter 24000 KHz, init 24000 KHz, kernel 0N/A)
aplll 816000 KHz
apllb 24000 KHz
dpll 800000 KHz
cpll 24000 KHz
gpll 800000 KHz
npll 600000 KHz
vpll 24000 KHz
aclk_perihp 133333 KHz
hclk_perihp 66666 KHz
pclk_perihp 33333 KHz
aclk_perilp0 266666 KHz
hclk_perilp0 88888 KHz
pclk_perilp0 44444 KHz
hclk_perilp1 100000 KHz
pclk_perilp1 50000 KHz
Net: No ethernet found.
Hit key to stop autoboot('CTRL+C'): 0
do_boot_rockchip: Could not find boot part
Checking for mmc dev 1...
Card did not respond to voltage select!
mmc_init: -95, time 9
starting USB...
USB0: USB EHCI 1.00
USB1: USB OHCI 1.0
USB2: USB EHCI 1.00
USB3: USB OHCI 1.0
scanning bus 0 for devices... 1 USB Device(s) found
scanning bus 1 for devices... 2 USB Device(s) found
scanning bus 2 for devices... 1 USB Device(s) found
scanning bus 3 for devices... 1 USB Device(s) found
scanning usb for storage devices... 0 Storage Device(s) found
Checking for usb dev 0...
Device 0: unknown device
Checking for mmc dev 0...
switch to partitions #0, OK
mmc0(part 0) is current device
Scanning mmc 0 for bootable partitions...
Scanning mmc 0:3 for extlinux or boot scripts...
Found /extlinux/extlinux.conf
Retrieving file: /extlinux/extlinux.conf
1992 bytes read in 67 ms (28.3 KiB/s)
select kernel
What I'm interested in, though, is the memory training speed.
Code:
channel 0 training pass!
channel 1 training pass!
change freq to 800MHz 1,0
Channel 0: LPDDR4,800MHz
Bus Width=32 Col=10 Bank=8 Row=15/15 CS=2 Die Bus-Width=16 Size=2048MB
Channel 1: LPDDR4,800MHz
Bus Width=32 Col=10 Bank=8 Row=15/15 CS=2 Die Bus-Width=16 Size=2048MB
256B stride
This is the final training pass I see in the uboot output.
Looking at the datsheet, the memory modules are either rated for 1600MHz or 1866MHz.
I've found that the RK3399 supports dynamic DRAM frequency scaling, but I haven't verified if this is working - I don't see anything about it in dmesg.
I see a peak of about 5.5GB/s running the "mbw" benchmark. At 800MHz on a 64 bit bus, I'd expect (800 * 2 * 64 / 8) = 12.8GB/s, which is consistent with a streaming copy bandwidth of around 5.5GB/s.
At 1600MHz, I'd expect to see 25.6GB/s - and I know there's display overhead, but for an optimized copy, it seems like we're not seeing the full performance of this system.
So, my questions:
0. Am I misreading the output/screwing up my math?
1. How can I verify the memory frequency in Linux?
2. Should uboot be setting the frequency to the maximum before handing off to a kernel that might not be adjusting it?
3. Should we have dynamic memory frequency stuff enabled in the kernel?
Thanks!
Well, darn. I was looking at the LPDDR4 datasheet, should have been looking at the RK3399 datasheet.
Per IRC, it just doesn't support running the memory bus up that high. Seems to be limited at 933 for DDR3, 800 for DDR4.
It appears the RK3399 is limited to an 800MHz memory channel on DDR4. It can do 933 on DDR3, and it might be worth messing with uboot to see if it can run 933 on DDR4, but there's apparently a hard check that doesn't allow it right now. It might be worth experimenting with.
(06-24-2020, 11:02 AM)Syonyk Wrote: It appears the RK3399 is limited to an 800MHz memory channel on DDR4. It can do 933 on DDR3, and it might be worth messing with uboot to see if it can run 933 on DDR4, but there's apparently a hard check that doesn't allow it right now. It might be worth experimenting with.
Should able to operate on 933MHz (PC-1866) LPDDR4. On the RockPro64 board, has been tested up to 1067MHz (PC-2133) LPDDR4 but no plan to release this driver.
Both ROckPro64 and Pinebook Pro PCB memory access simulation has been tested up to PC-2400.
Now I have an excuse to learn to build uboot and ATF for the PBP. This looks like a binary blob for... one of the parts in the early boot process, based on the strings and where they show up in boot. Are there any particular license restrictions that apply to anything built with this?
It was unclear what the limit on the RK3399 was - the spec sheet seemed to imply 933MHz for LPDDR4, but the uboot source seemed to have a check for LPDDR4 that would cut it down to 800MHz. No idea on the history of that, but it sounds like 933MHz is fully within SoC and board specifications on the PBP?