08-28-2019, 10:51 AM
(This post was last modified: 08-29-2019, 04:28 AM by Arwen.
Edit Reason: Added Epson camera
)
Ignoring the warm / heated discussion, here are my comments;
My first NAS used a single core SPARCv8, (aka 32 bit), somewhat embedded processor running Linux, (Infrant ReadyNAS 1000s).
The SPARC T1 can be used embedded, just select the number of cores and number of threads per core needed. It's designed to
be upto 8 cores, with upto 4 threads per core, (for 32 threads). Of course, the SPARC T1 is dated, it's just one of the first multi-threaded
OpenSource processors released.
Or you could take the Epson PhotoPC 500 camera. It was my first and only digital camera, the rest were multi-function devices like Android tablets or phones. If I remember correctly, the PhotoPC 500 used a SPARC processor.
Stock PCs, and any PC compatible hardware, (embedded or not), will have legacy things that would not be needed on a new design.
RISC-V has certain advantages over older designs. The "thumb" instructions, (using ARM terminology for compressed / shorter / limited
instructions), on RISC-V can be mixed with regular instructions. Even to the point of having the compiler or assembler prefer them over their
regular counterparts! This is because these "thumb", (RISC-V uses compressed wording), are reserved in the overall instruction bit map.
Further, if a CPU designer does not need a specific set of instructions, like floating point, they can be left off. Or new instructions implemented
for specialized designs. I would personally like checksum, compression & encryption instructions that OpenZFS uses, added for a NAS
processor.
Today, most laptops or desktops are 64 bit to allow for larger than 4GB of memory. But, the old Intel designed arch. requires 16 bit & 32 bit
backward compatibility. We all know what happened when Intel tried to force 64 bit only CPUs on us, they sank like the Titanic, (which is why
a common name for the Itanium is Itanic).
That happened about 20 years ago. Now we have much more tools available, (both software & hardware), so a brand new CPU type, like
RISC-V64GC, can be made completely open, but still very usable. That means we can try and avoid the Intel security Tax on performance,
(Meltdown, TLBleed, ForeShadow and the ever popular Spectre).
What I would like to see is an open sourced CPU, (like the RISC-V), made for desktops and laptops, that anyone can view the source code.
Perhaps only a tiny percent of the people who view the CPU source code would understand it. But, hundreds if not thousands of people
could make comments and potentially drive improvements. I've seen, (and been a very light weight submitter to), OpenSource sofware
that has hundreds of participants. Some are core developers, others, (again like me), were just fringe assistants.
All that said, I have hopes for a RISC-V desktop of reasonable price / performance, (or laptop). But I don't see it happening for another 2
years at a minimum.
Edit: Forgot to mention Epson PhotoPC 500 which uses embedded SPARC processor
My first NAS used a single core SPARCv8, (aka 32 bit), somewhat embedded processor running Linux, (Infrant ReadyNAS 1000s).
The SPARC T1 can be used embedded, just select the number of cores and number of threads per core needed. It's designed to
be upto 8 cores, with upto 4 threads per core, (for 32 threads). Of course, the SPARC T1 is dated, it's just one of the first multi-threaded
OpenSource processors released.
Or you could take the Epson PhotoPC 500 camera. It was my first and only digital camera, the rest were multi-function devices like Android tablets or phones. If I remember correctly, the PhotoPC 500 used a SPARC processor.
Stock PCs, and any PC compatible hardware, (embedded or not), will have legacy things that would not be needed on a new design.
RISC-V has certain advantages over older designs. The "thumb" instructions, (using ARM terminology for compressed / shorter / limited
instructions), on RISC-V can be mixed with regular instructions. Even to the point of having the compiler or assembler prefer them over their
regular counterparts! This is because these "thumb", (RISC-V uses compressed wording), are reserved in the overall instruction bit map.
Further, if a CPU designer does not need a specific set of instructions, like floating point, they can be left off. Or new instructions implemented
for specialized designs. I would personally like checksum, compression & encryption instructions that OpenZFS uses, added for a NAS
processor.
Today, most laptops or desktops are 64 bit to allow for larger than 4GB of memory. But, the old Intel designed arch. requires 16 bit & 32 bit
backward compatibility. We all know what happened when Intel tried to force 64 bit only CPUs on us, they sank like the Titanic, (which is why
a common name for the Itanium is Itanic).
That happened about 20 years ago. Now we have much more tools available, (both software & hardware), so a brand new CPU type, like
RISC-V64GC, can be made completely open, but still very usable. That means we can try and avoid the Intel security Tax on performance,
(Meltdown, TLBleed, ForeShadow and the ever popular Spectre).
What I would like to see is an open sourced CPU, (like the RISC-V), made for desktops and laptops, that anyone can view the source code.
Perhaps only a tiny percent of the people who view the CPU source code would understand it. But, hundreds if not thousands of people
could make comments and potentially drive improvements. I've seen, (and been a very light weight submitter to), OpenSource sofware
that has hundreds of participants. Some are core developers, others, (again like me), were just fringe assistants.
All that said, I have hopes for a RISC-V desktop of reasonable price / performance, (or laptop). But I don't see it happening for another 2
years at a minimum.
Edit: Forgot to mention Epson PhotoPC 500 which uses embedded SPARC processor
--
Arwen Evenstar
Princess of Rivendale
Arwen Evenstar
Princess of Rivendale