Star64: jtag debugging?
#1
I'm thinking of getting a Star64 to do some practical learning about operating system development and I haven't been able to find some clear/simple information about compatible equipment and the process for setting up a jtag debugging environment. Please note that my experience is mostly with software and I am really, really new to working so close to the hardware.

The Star64 schematics show GPIO pins 0 to 4 for debug trace and pins 9 to 13 for jtag HIFI4 (audio DSP). From the very little that I know about jtag this is the minimum number of pins - so minimum amount of jtag functionality.

I have been looking at the Segger J-Link Edu because it has support for the U74 and E24 SiFive cores in the Star64, but I'm not sure if it is a good choice.

Has anyone setup jtag debugging for the Star64? What hardware/software are you using and can you recommend a beginners guide that can get me started?
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#2
I am using a j-link edu with my star64 board. I am using a macbook pro with my jlink edu. I also connected to the uart pins on the star64.



Here are the pins that need to be connected from the edu to the star64 gpio pins:



JLinkEdu pin    Star64 gpio pin



1               40

3               36

5               38

7               35

9               37

1               2


I couldn't figure out how to use the jlinkexe software to connect to the different cores of the jh7110.



I WAS able to use openocd to connect and see all the cores. I was able to load different programs onto different cores.



I used openocd with the following text in a config file:



>>>>

// config.tcl

adapter driver jlink



reset_config trst_only



transport select jtag



adapter speed 4000



jtag newtap e24 cpu -irlen 5

jtag newtap u74 cpu -irlen 5



#target create e24.cpu0 riscv -chain-position e24.cpu -coreid 0

target create u74.cpu0 riscv -chain-position u74.cpu -coreid 0 -rtos hwthread

target create u74.cpu1 riscv -chain-position u74.cpu -coreid 1

target create u74.cpu2 riscv -chain-position u74.cpu -coreid 2

target create u74.cpu3 riscv -chain-position u74.cpu -coreid 3

target create u74.cpu4 riscv -chain-position u74.cpu -coreid 4

#target smp u74.cpu0 u74.cpu1 u74.cpu2 u74.cpu3 u74.cpu4



init
>>>>



There isn't much general documentation for the JH7110. I did write a simple assembly program that wrote to the serial board.

I was able load the program onto the board using openocd. It was fun seeing 4 cores all writing to the serial port at the same time!
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