Revisiting RK3399 LPDDR speeds

[Syonyk]

As the world turns loony about computing, I've decided it's a good time to get back into some low level ARM hacking, and since I've been daily driving the PBP for a while (it's boring, it works, if you've not flashed the recent trackpad firmware go do so because it makes the trackpad absolutely acceptable), I figure I should hack on it a bit more.  That a friend shipped me a spare one as dev hardware doesn't hurt...

Anyway, some while ago, I was curious as to the DRAM training speed for the PBP: https://forum.pine64.org/showthread.php?tid=10398

The long and short of it is that the PBP runs the LPDDR4 at 800MHz.  Buuuut, from that other thread, maybe it can run faster?

I imagine most of us are running the bootloader from here: https://gitlab.manjaro.org/manjaro-arm/p...ookpro-bsp

Trimming the training a bit, you get:

Code:

DDR Version 1.15 20181010
In
Channel 0: LPDDR4,50MHz
...
Bus Width=32 Col=10 Bank=8 Row=15/15 CS=2 Die Bus-Width=16 Size=2048MB
Channel 1: LPDDR4,50MHz
...
Bus Width=32 Col=10 Bank=8 Row=15/15 CS=2 Die Bus-Width=16 Size=2048MB
...
channel 0 training pass!
channel 1 training pass!
change freq to 400MHz 0,1
...
channel 0 training pass!
channel 1 training pass!
change freq to 800MHz 1,0
ch 0 ddrconfig = 0x101, ddrsize = 0x2020
ch 1 ddrconfig = 0x101, ddrsize = 0x2020
pmugrf_os_reg[2] = 0x3AA1FAA1, stride = 0xD
OUT

DDR version 1.15, 2018/10/10, trains in at 800MHz.  As generally acknowledge and expected.

@tllim offered up a v1.11 933MHz driver in the other thread that was claimed to run the DDR4 faster.

I built it thusly, from the rkbin tree:

Code:

tools/mkimage -n rk3399 -T rksd -d ../rk3399_ddr_933MHz_v1.11.bin idbloader.img
cat bin/rk33/rk3399_miniloader_v1.26.bin > idbloader.img

And flashed it to the SD card.  Result:

Code:

DDR Version 1.11 20180509
In
Channel 0: LPDDR4,50MHz
...
Bus Width=32 Col=10 Bank=8 Row=15/15 CS=2 Die Bus-Width=16 Size=2048MB
Channel 1: LPDDR4,50MHz
...
Bus Width=32 Col=10 Bank=8 Row=15/15 CS=2 Die Bus-Width=16 Size=2048MB
...
channel 0 training pass!
channel 1 training pass!
change freq to 400MHz 0,1
...
channel 0 training pass!
channel 1 training pass!
change freq to 800MHz 1,0
ch 0 ddrconfig = 0x101, ddrsize = 0x2020
ch 1 ddrconfig = 0x101, ddrsize = 0x2020
pmugrf_os_reg[2] = 0x3AA1FAA1, stride = 0xD
OUT

I'm confident that I've flashed the new .bin file, because it's version 1.11 - vs 1.15 from earlier.  However, no signs of the 933MHz memory I was promised.

However, exploring yet further, there's a newer file in the rkbin tree:

rk3399_ddr_933MHz_v1.25.bin

Well, let's try it out!

And that does something far more interesting looking!

Code:

DDR Version 1.25 20210517
In
...
channel 0 training pass!
channel 1 training pass!
change freq to 416MHz 0,1
Channel 0: LPDDR4,416MHz
Bus Width=32 Col=10 Bank=8 Row=15/15 CS=2 Die Bus-Width=16 Size=2048MB
Channel 1: LPDDR4,416MHz
Bus Width=32 Col=10 Bank=8 Row=15/15 CS=2 Die Bus-Width=16 Size=2048MB
...
channel 0 training pass!
channel 1 training pass!
channel 0, cs 0, advanced training done
channel 0, cs 1, advanced training done
channel 1, cs 0, advanced training done
channel 1, cs 1, advanced training done
change freq to 856MHz 1,0
ch 0 ddrconfig = 0x101, ddrsize = 0x2020
ch 1 ddrconfig = 0x101, ddrsize = 0x2020
pmugrf_os_reg[2] = 0x3AA1FAA1, stride = 0xD
ddr_set_rate to 328MHZ
ddr_set_rate to 666MHZ
ddr_set_rate to 928MHZ
channel 0, cs 0, advanced training done
channel 0, cs 1, advanced training done
channel 1, cs 0, advanced training done
channel 1, cs 1, advanced training done
ddr_set_rate to 416MHZ, ctl_index 0
ddr_set_rate to 856MHZ, ctl_index 1
support 416 856 328 666 928 MHz, current 856MHz
OUT

Version 1.25, as expected... and it manages to find some new rates, including 928MHz - which is close to 933Mhz.

However, it then seems to settle in at 856MHz, vs the maximum rate found.

At this point, I have my suspicions that this then somehow interacts with the dynamic DRAM scaling features that rk3399 has in the Linux kernel - but I've not gotten quite that far.

Does anyone have any handy tips on how to get this to actually leave 928MHz the current speed, or how to get that selected later at runtime?  Not sure if I'm barking down the right path here or not.

---

There is then this document: https://usermanual.wiki/Document/Rockchi...34866/view

It describes how to set up DDR frequency scaling in Linux.

I cannot find any evidence of those dtb elements being present in the rk3399 dts section of the kernel.  Is there a fork that has them?  Theoretically the kernel has the rockchip frequency scaling by 5.x, given it was put in back in the 4.x series...

[Syonyk]

I *think* the required bits for DDR frequency scaling are in the kernel, but nobody has shipped DTS files with any of the required sections.

It also just makes a call down into the appropriate ATF layer to do the actual scaling, so requires support down there as well. I would hope the BSP UBoot/ATF have support, but I've not verified it yet. Will keep poking...