03-21-2021, 12:01 PM
(03-20-2021, 05:47 AM)dsimic Wrote: All that could be doable, but it all depends on the way quad-SPI IP core actually works and presents itself. More information should be available from the publicly available source code; I guess it's time to dig into it.
For sure - and I suppose we may be the first people to even try to do such a thing, despite what is written in the source. Bare in mind the BL602 is a very new device. In theory though, even if the DMA buffers cannot be remapped, we can enable any chip we like. I can't see how such a thing can be prevented.
(03-20-2021, 05:47 AM)dsimic Wrote: I would like to see Pine64 onboard this project/initiative, but for some reason they remain silent to the community inquiries, as we've already discussed. Regarding the new RISC-V SBC, the whole thing sounds really good; it should bring "full-fledged" RISC-V to the masses.
100%. Before pouring time and effort into this, I really want to hear from them. There's zero point in us guessing at what the bigger picture may be, maybe Pine64 has zero interest in such things. We just don't know.
(03-20-2021, 05:47 AM)dsimic Wrote: I hope you're right and there are more people sharing the vision and excitement. For example, it could also be used as a WiFi wardriving device or a WiFi IDS sensor capable of storing packet dumps locally.
Basically anything that could involve connectivity and reliable/secure storage. And this is just an immediate outcome of having a slow storage device - when it speeds up we could have even more exciting potential projects.