03-17-2021, 07:02 PM
(03-17-2021, 02:04 PM)Julius_GU Wrote: Excuse me if I misunderstood your question, but I think it is on the IC itself
https://github.com/pine64/bl602-docs/blo...1.6_en.pdf (PAGE 6)
So on page 7 you have "XIP QSPI/SPI Flash with hardware decryption support" and "Embedded Flash (Optional)" - it's not obvious to me that the embedded flash operates through the XIP SPI section. I looked through the whole document, but couldn't see anything that for sure showed that the optional flash is on the XIP SPI bus.
If it was on the XIP SPI bus, that would raise different questions, like how it would boot up when there are up to four devices? Which one does it enable before it's loaded it's first byte of code?
By the way, I believe the limit of four XIP SPI devices could just be the four DMA buffers, in which case they could be remapped in realtime... With a given RAID configuration we could make guarantees about which flash device will be active when... Experiments would be needed of course.