Boinc issue
#2
Per the spec for the big.LITTLE CPU cluster architecture, only one "side" (big, or little) is allowed to be active at one time.

The "sides" share one memory space and can easily toggle tasks between the two sides, which is what it was designed for.
But the tasks either toggle all the way to "big", or all the way to "LITTLE", and cannot straddle the two.

It allows a developer to swap tasks between lower power consumption and higher power consumption, on purpose, when needed, to achieve more granular power management, than say forcefully frequency-cycling the individual cores within the 2 clusters.

So anyway, always having either: "4 out of 6", or "2 out of 6", CPUs active at any given time, is 100% correct.
You will never, ever see even 5 out of 6.

The "big" cores are Cortex A57 and "LITTLE" cores are Cortex A53, and that probably has something to do with it.

The "S" in "SMP" ("symmetric" multiprocessing) is the reason for this - this SoC is asymmetrical.
This big.LITTLE architecture is more like forced "AMP", and is wholly incompatible with the concept of "SMP".


Messages In This Thread
Boinc issue - by Fabien - 12-12-2018, 03:08 AM
RE: Boinc issue - by fosf0r - 12-12-2018, 12:28 PM
RE: Boinc issue - by p12 - 12-14-2018, 05:38 AM
RE: Boinc issue - by fosf0r - 12-19-2018, 10:06 AM
RE: Boinc issue - by Fabien - 12-13-2018, 08:21 AM
RE: Boinc issue - by fosf0r - 12-14-2018, 08:29 AM
RE: Boinc issue - by Fabien - 12-17-2018, 03:24 AM
RE: Boinc issue - by Fabien - 12-19-2018, 02:46 AM

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