LACK OF REVISION CONTROL ON ROCK PRO 64

[Bullet64]

SATA-Card is detected after removing resistor.

Code:

rock64@rockpro64:~$ uname -a
Linux rockpro64 4.4.126-rockchip-ayufan-257 #1 SMP Sun Jun 10 18:30:43 UTC 2018 aarch64 aarch64 aarch64 GNU/Linux

Code:

rock64@rockpro64:~$ lspci
00:00.0 PCI bridge: Rockchip Inc. RK3399 PCI Express Root Port Device 0100
01:00.0 SATA controller: ASMedia Technology Inc. ASM1062 Serial ATA Controller (rev 02)

lspci -vvv

Code:

rock64@rockpro64:~$ sudo lspci -vvv
[sudo] password for rock64:
00:00.0 PCI bridge: Rockchip Inc. RK3399 PCI Express Root Port Device 0100 (prog-if 00 [Normal decode])
    Control: I/O- Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- DisINTx+
    Status: Cap+ 66MHz- UDF- FastB2B- ParErr- DEVSEL=fast >TAbort+ <TAbort+ <MAbort+ >SERR+ <PERR+ INTx-
    Latency: 0
    Interrupt: pin A routed to IRQ 238
    Bus: primary=00, secondary=01, subordinate=01, sec-latency=0
    I/O behind bridge: 00000000-00000fff
    Memory behind bridge: fa000000-fa0fffff
    Prefetchable memory behind bridge: 00000000-000fffff
    Secondary status: 66MHz- FastB2B- ParErr- DEVSEL=fast >TAbort- <TAbort- <MAbort- <SERR- <PERR-
    BridgeCtl: Parity- SERR- NoISA- VGA- MAbort- >Reset- FastB2B-
        PriDiscTmr- SecDiscTmr- DiscTmrStat- DiscTmrSERREn-
    Capabilities: [80] Power Management version 3
        Flags: PMEClk- DSI- D1+ D2- AuxCurrent=0mA PME(D0+,D1+,D2-,D3hot+,D3cold-)
        Status: D0 NoSoftRst+ PME-Enable- DSel=0 DScale=0 PME+
    Capabilities: [90] MSI: Enable+ Count=1/1 Maskable+ 64bit+
        Address: 00000000fee30040  Data: 0000
        Masking: 00000000  Pending: 00000000
    Capabilities: [b0] MSI-X: Enable- Count=1 Masked-
        Vector table: BAR=0 offset=00000000
        PBA: BAR=0 offset=00000008
    Capabilities: [c0] Express (v2) Root Port (Slot+), MSI 00
        DevCap:    MaxPayload 256 bytes, PhantFunc 0
            ExtTag- RBE+
        DevCtl:    Report errors: Correctable+ Non-Fatal+ Fatal+ Unsupported+
            RlxdOrd+ ExtTag- PhantFunc- AuxPwr- NoSnoop+
            MaxPayload 128 bytes, MaxReadReq 512 bytes
        DevSta:    CorrErr- UncorrErr- FatalErr- UnsuppReq- AuxPwr- TransPend-
        LnkCap:    Port #0, Speed 5GT/s, Width x4, ASPM L1, Exit Latency L0s <256ns, L1 <8us
            ClockPM- Surprise- LLActRep- BwNot+ ASPMOptComp+
        LnkCtl:    ASPM Disabled; RCB 64 bytes Disabled- CommClk-
            ExtSynch- ClockPM- AutWidDis- BWInt+ AutBWInt+
        LnkSta:    Speed 5GT/s, Width x1, TrErr- Train- SlotClk- DLActive- BWMgmt- ABWMgmt-
        SltCap:    AttnBtn- PwrCtrl- MRL- AttnInd- PwrInd- HotPlug- Surprise-
            Slot #0, PowerLimit 0.000W; Interlock- NoCompl-
        SltCtl:    Enable: AttnBtn- PwrFlt- MRL- PresDet- CmdCplt- HPIrq- LinkChg-
            Control: AttnInd Off, PwrInd Off, Power+ Interlock-
        SltSta:    Status: AttnBtn- PowerFlt- MRL+ CmdCplt- PresDet- Interlock-
            Changed: MRL- PresDet- LinkState-
        RootCtl: ErrCorrectable- ErrNon-Fatal- ErrFatal- PMEIntEna+ CRSVisible-
        RootCap: CRSVisible-
        RootSta: PME ReqID 0000, PMEStatus- PMEPending-
        DevCap2: Completion Timeout: Range B, TimeoutDis+, LTR+, OBFF Via message ARIFwd+
        DevCtl2: Completion Timeout: 50us to 50ms, TimeoutDis-, LTR-, OBFF Disabled ARIFwd-
        LnkCtl2: Target Link Speed: 5GT/s, EnterCompliance- SpeedDis-
             Transmit Margin: Normal Operating Range, EnterModifiedCompliance- ComplianceSOS-
             Compliance De-emphasis: -6dB
        LnkSta2: Current De-emphasis Level: -6dB, EqualizationComplete-, EqualizationPhase1-
             EqualizationPhase2-, EqualizationPhase3-, LinkEqualizationRequest-
    Capabilities: [100 v2] Advanced Error Reporting
        UESta:    DLP- SDES- TLP- FCP- CmpltTO- CmpltAbrt- UnxCmplt- RxOF- MalfTLP- ECRC- UnsupReq- ACSViol-
        UEMsk:    DLP- SDES- TLP- FCP- CmpltTO- CmpltAbrt- UnxCmplt- RxOF- MalfTLP- ECRC- UnsupReq- ACSViol-
        UESvrt:    DLP+ SDES+ TLP- FCP+ CmpltTO- CmpltAbrt- UnxCmplt- RxOF+ MalfTLP+ ECRC- UnsupReq- ACSViol-
        CESta:    RxErr- BadTLP- BadDLLP- Rollover- Timeout- NonFatalErr-
        CEMsk:    RxErr- BadTLP- BadDLLP- Rollover- Timeout- NonFatalErr+
        AERCap:    First Error Pointer: 00, GenCap+ CGenEn- ChkCap+ ChkEn-
    Capabilities: [274 v1] Transaction Processing Hints
        Interrupt vector mode supported
        Device specific mode supported
        Steering table in TPH capability structure
    Kernel driver in use: pcieport

01:00.0 SATA controller: ASMedia Technology Inc. ASM1062 Serial ATA Controller (rev 02) (prog-if 01 [AHCI 1.0])
    Subsystem: ASMedia Technology Inc. ASM1062 Serial ATA Controller
    Control: I/O- Mem- BusMaster- SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- DisINTx-
    Status: Cap+ 66MHz- UDF- FastB2B- ParErr- DEVSEL=fast >TAbort- <TAbort- <MAbort- >SERR- <PERR- INTx-
    Interrupt: pin A routed to IRQ 237
    Region 0: I/O ports at <unassigned> [disabled]
    Region 1: I/O ports at <unassigned> [disabled]
    Region 2: I/O ports at <unassigned> [disabled]
    Region 3: I/O ports at <unassigned> [disabled]
    Region 4: I/O ports at <unassigned> [disabled]
    Region 5: Memory at fa010000 (32-bit, non-prefetchable) [disabled] [size=512]
    [virtual] Expansion ROM at fa000000 [disabled] [size=64K]
    Capabilities: [50] MSI: Enable- Count=1/1 Maskable- 64bit-
        Address: 00000000  Data: 0000
    Capabilities: [78] Power Management version 3
        Flags: PMEClk- DSI- D1- D2- AuxCurrent=0mA PME(D0-,D1-,D2-,D3hot-,D3cold-)
        Status: D0 NoSoftRst- PME-Enable- DSel=0 DScale=0 PME-
    Capabilities: [80] Express (v2) Legacy Endpoint, MSI 00
        DevCap:    MaxPayload 512 bytes, PhantFunc 0, Latency L0s <1us, L1 <8us
            ExtTag- AttnBtn- AttnInd- PwrInd- RBE+ FLReset-
        DevCtl:    Report errors: Correctable- Non-Fatal- Fatal- Unsupported-
            RlxdOrd+ ExtTag- PhantFunc- AuxPwr- NoSnoop+
            MaxPayload 128 bytes, MaxReadReq 512 bytes
        DevSta:    CorrErr+ UncorrErr- FatalErr- UnsuppReq- AuxPwr- TransPend-
        LnkCap:    Port #1, Speed 5GT/s, Width x1, ASPM not supported, Exit Latency L0s unlimited, L1 <2us
            ClockPM- Surprise- LLActRep- BwNot- ASPMOptComp-
        LnkCtl:    ASPM Disabled; RCB 64 bytes Disabled- CommClk-
            ExtSynch- ClockPM- AutWidDis- BWInt- AutBWInt-
        LnkSta:    Speed 5GT/s, Width x1, TrErr- Train- SlotClk+ DLActive- BWMgmt- ABWMgmt-
        DevCap2: Completion Timeout: Range ABC, TimeoutDis+, LTR-, OBFF Not Supported
        DevCtl2: Completion Timeout: 50us to 50ms, TimeoutDis-, LTR-, OBFF Disabled
        LnkCtl2: Target Link Speed: 5GT/s, EnterCompliance- SpeedDis-
             Transmit Margin: Normal Operating Range, EnterModifiedCompliance- ComplianceSOS-
             Compliance De-emphasis: -6dB
        LnkSta2: Current De-emphasis Level: -6dB, EqualizationComplete-, EqualizationPhase1-
             EqualizationPhase2-, EqualizationPhase3-, LinkEqualizationRequest-
    Capabilities: [100 v1] Virtual Channel
        Caps:    LPEVC=0 RefClk=100ns PATEntryBits=1
        Arb:    Fixed- WRR32- WRR64- WRR128-
        Ctrl:    ArbSelect=Fixed
        Status:    InProgress-
        VC0:    Caps:    PATOffset=00 MaxTimeSlots=1 RejSnoopTrans-
            Arb:    Fixed- WRR32- WRR64- WRR128- TWRR128- WRR256-
            Ctrl:    Enable+ ID=0 ArbSelect=Fixed TC/VC=ff
            Status:    NegoPending- InProgress-

But the card don't detect any HDD / SDD   But I do not know if it's a hard or software problem.

[Luke]

NVMe works, so that leads me to think software.

[pfeerick]

Indeed, its a resistor - was awfully tired yesterday when responding

Sorry Luke... I saw that this morning, but opted to leave it alone!   And yes, reflowing with new solder, especially with some decent lead solder instead of this lead-free nonsense is essential if you want things to behave!  

NVMe works, so that leads me to think software.

True. Especially as the SATA card is detected on its own, but the NVMe one isn't, due to it basically just being a holder for the NVMe drive.

[lucho]

Excuse me, which resistor on the schematic (Sheet number, R number) is removed?

[wis]

R56 or R57 (sht. 15)? Something to do with PERST#?

[Bullet64]

http://files.pine64.org/doc/rockpro64/ro...20-SCH.pdf


Sheet 27

R89538

Pin EN

No guarantee, at your own risk!

[pfeerick]

For the visual reference in addition:
   

It looks like it would either hold what looks to be a 12 -> 3v3 regulators enable pin either on or off, rather than it being solely controllable by GPIO1_D0 on the RK3399. Hard to tell exactly as I can't find a datasheet for that part.

[lucho]

Thanks for the information! Unfortunately, I can't find the datasheet of the TCS4484B voltage converter, but from the schematic, one can see that this is the resistor was a part of a voltage divider to reduce the level of the PCIE_PWR signal on the "enable" line (EN) of the TCS4484B in half. (Probably this EN line is connected internally to a base of an NPN transistor whose emitter is grounded.) I don't know the voltage level of this signal when it's in HIGH State, but on sheet 15 there is a note: "RK3399 part E is 1.8V/3.0V mode". Perhaps at first it was assumed (or determined) that the HIGH State level of this signal would be 3.3 V, but then it turned out to be just 1.5 (or 1.8) V, which, divided in half by the aforementioned voltage divider, turned out to be insufficient to enable the TCS4484B, so it become necessary to get rid of the voltage divider by removing R895381 and connecting the PCIE_PWR to the EN pin of the TCS4484B only via R223. Is this explanation of mine close to the truth?

[Bullet64]

Nice explanation. I think it's so.

What i can tell is, for me it work's. Only with PCIe NVMe Card. SATA Card don't work.

[pfeerick]

Thanks for the information! Unfortunately, I can't find the datasheet of the TCS4484B voltage converter, but from the schematic, one can see that this is the resistor was a part of a voltage divider to reduce the level of the PCIE_PWR signal on the "enable" line (EN) of the TCS4484B in half. (Probably this EN line is connected internally to a base of an NPN transistor whose emitter is grounded.) I don't know the voltage level of this signal when it's in HIGH State, but on sheet 15 there is a note: "RK3399 part E is 1.8V/3.0V mode". Perhaps at first it was assumed (or determined) that the HIGH State level of this signal would be 3.3 V, but then it turned out to be just 1.5 (or 1.8) V, which, divided in half by the aforementioned voltage divider, turned out to be insufficient to enable the TCS4484B, so it become necessary to get rid of the voltage divider by removing R895381 and connecting the PCIE_PWR to the EN pin of the TCS4484B only via R223. Is this explanation of mine close to the truth?

Yup, that makes sense. If the 'enable' signal is a positive signal, it has to be a voltage divider. It can only be that or a pull-down resistor to ensure a known state before the SoC GPIOs are configured, which is pulling down too hard. That fact that it looks like it may be a NC part in the future make it look more like a voltage divider that's not necessary. Hopefully the sata problem is just driver related now, as the SATA card does appear on the PCI bus so it is being powered and is talking to the rockpro64... or at least the controller is to some extent.