07-28-2016, 07:19 PM
(This post was last modified: 07-28-2016, 07:25 PM by martinayotte.)
For interrupt, following the specs sheet, it was pretty easy to determine that the s_twi is 0x2c (76 in the specs, but offsetted by 32) since the s_uart is 0x26 (70 in specs) (except if the previous offsetting is wrong), maybe I should try to get rid of this offset which I don't know where it is coming from.
Problem can also be from clock and reset, which are not using apb0_gates/apb0_reset like other sunxi such H3 where the I2C on i2c@01f02400 is working.
I hate this PineA64 DTS since it is coming from a decompiled version from AllWinner and doesn't follow rules used in Mainline, where apb0_gates/apb0_reset doesn't even exist.
EDIT: I've checked the interrupt on H3, and it is really 0x2C (76 with offset of 32). Som it must be something else, the clock or the reset.
Problem can also be from clock and reset, which are not using apb0_gates/apb0_reset like other sunxi such H3 where the I2C on i2c@01f02400 is working.
I hate this PineA64 DTS since it is coming from a decompiled version from AllWinner and doesn't follow rules used in Mainline, where apb0_gates/apb0_reset doesn't even exist.
EDIT: I've checked the interrupt on H3, and it is really 0x2C (76 with offset of 32). Som it must be something else, the clock or the reset.