No boot after Manjaro flash

[thebladerunner]

I don’t know why people try to reflash the SPI memory either. I did not intentionally do that. The update to Manjaro seemed to be the source of my problem. 

There are some differences in your proposed method. I’ll try that later today and see if I can resurrect this PBP.

I suspect that you are chasing a red herring (that is, SPI is blank)
My guess is that the manjaro update has a new kernel, and ALSO a new dtb
And that, I suspect is the problem
You said you have serial connection?
Does it display the start of uboot?
If so, remove ALL media, do you get the same thing?
If yes, then uboot is on SPI,,,,, if no, then problem is on emmc
And, for that matter, only mrfixit actually writes the uboot to the 1st 16M (in an update)
(nearly ALL images have the 1st 16M populated, as part of the image)
manjaro just dumps idbloader and uboot.itb into /boot,
you are supposed to do the actual dd write yourself, manually
ALSO (emmc in usb carrier),,, ls -l boot/dtbs/rockchip/*pinebook-pro*
If there is an older, try a rename (current -> *.bad,,, older -> current)

The EMMC module is physically removed as well as the switch turned off. There is no SD card or USB installed.

Below is what I'm getting from the serial connection. It repeats continuously. Also, I've tried every version I have found of entering the Maskrom mode and cannot get there.

U-Boot SPL board init

U-Boot SPL 2017.09-rockchip-ayufan-1065-g95f6152134 (Apr 06 2020 - 08:11:31)
booted from SPI flash
Trying to boot from SPI
"Synchronous Abort" handler, esr 0x02000000
ELR:    10000
LR:      18d8
x 0: 0000000000400000 x 1: 0000000000000000
x 2: 0000000000010000 x 3: 0000000000400180
x 4: 0000000000000000 x 5: 0000000000000000
x 6: 0000000000000030 x 7: 0000000000400188
x 8: 00000000000003ec x 9: 0000000000000000
x10: 00000000005ffc0c x11: 00000000001ffac0
x12: 00000000000003b5 x13: 00000000000003a8
x14: 00000000005ffc5c x15: 00000000001ffac0
x16: 0000000000000000 x17: 0000000000000000
x18: 00000000005ffea0 x19: 000000000000f1c8
x20: 000000000000f1b0 x21: 0000000000000000
x22: 00000000005ffe70 x23: 00000000005ffe58
x24: 000000000000ccac x25: 000000000000cc94
x26: 000000000000f000 x27: 00000000deadbeef
x28: 0000000000000490 x29: 00000000005ffde0

Resetting CPU ...

DDR Version 1.19 20190305
In
soft reset
SRX
channel 0
CS = 0
MR0=0xB9
MR4=0x3
MR5=0xFF
MR8=0x10
MR12=0x72
MR14=0x72
MR18=0x0
MR19=0x0
MR24=0x8
MR25=0xFF
channel 1
CS = 0
MR0=0xB9
MR4=0x3
MR5=0xFF
MR8=0x10
MR12=0x72
MR14=0x72
MR18=0x0
MR19=0x0
MR24=0x8
MR25=0xFF
channel 0 training pass!
channel 1 training pass!
change freq to 400MHz 0,1
channel 0
CS = 0
MR0=0xB9
MR4=0x3
MR5=0xFF
MR8=0x10
MR12=0x72
MR14=0x72
MR18=0x0
MR19=0x0
MR24=0x8
MR25=0xFF
channel 1
CS = 0
MR0=0xB9
MR4=0x3
MR5=0xFF
MR8=0x10
MR12=0x72
MR14=0x72
MR18=0x0
MR19=0x0
MR24=0x8
MR25=0xFF
channel 0 training pass!
channel 1 training pass!
change freq to 800MHz 1,0
Channel 0: LPDDR4,800MHz
Bus Width=32 Col=10 Bank=8 Row=16 CS=1 Die Bus-Width=16 Size=2048MB
Channel 1: LPDDR4,800MHz
Bus Width=32 Col=10 Bank=8 Row=16 CS=1 Die Bus-Width=16 Size=2048MB
256B stride
ch 0 ddrconfig = 0x101, ddrsize = 0x40
ch 1 ddrconfig = 0x101, ddrsize = 0x40
pmugrf_os_reg[2] = 0x32C1F2C1, stride = 0xD
OUT