CPU Architecture
#1
I am unfamiliar with architecture that uses two separate and different CPU's this way. Processing wise, what is going on here? Thanks.

 Cortex-A72 (big cluster):

    Dual-core Cortex-A72 up to 2.0GHz CPU
    Superscalar, variable-length, out-of-order pipeline
    L1 cache 48KB Icache and 32KB Dcache for each A72
    L2 cache 1024KB for big cluster

Cortex-A53 (little cluster):

    Quad-core Cortex-A53 up to 1.5GHz CPU
    In-order pipeline with symmetric dual-issue of most instructions
    L1 cache 32KB Icache and 32KB Dcache for each A53
    L2 cache 512KB for little cluster
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