eMMC doesn't work after kernel start
#1
Hi. I am trying to install ArchLinuxARM on the emmc module to boot Rock64 v2.0 board. When i'm trying the following happens.

1. I flash three u-boot images, as in tutorial. It seems working, because...

2. When i power up the Rock64, it writes some usuall messages to the UART on the. So, as i understand, u-boot images are being loaded successfully, partition table is being read successfully, so the Linux Kernel starts and writes a lot of info to the UART.

3. But when the kernel attempts to mount root file system, it can't do this and throws me to the emergency shell. Where i try to read from emmc, e.g., using the command
Code:
dd if=/dev/mmcblk1 of=/dev/stdout count=10
i get nothing. When i'm trying to

Code:
hexdump /dev/mmcblk1

i get I/O error.

4. So... What is wrong? It does not looks like as hardware error. Because u-boot somehow figures out the correct PARTUUID for the partition and passes it to the kernel. So, the partition table sectors are readable, but no to the kernel... May be some driver option will help?

Screenlog is here http://k.imm.uran.ru/tmp/screenlog.0

Thanks in advance
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#2
UPDATE: I've just flashed Android 9.0 image to the eMMC module, and it successfully booted. So the problem is not with hardware.
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#3
I've tried to flash and boot Bionic. It has booted successfully. I've collected logs of Android and Bionic boots, which can be downloaded from here: http://k.imm.uran.ru/tmp/screenlog.tar.xz

Excerpt about MMC from different boots.

Bionic
Code:
board_init_sdmmc_pwr_en
booted from eMMC
Trying to boot from MMC1
MMC:   [email protected]: 0, [email protected]: 1
mmc0(part 0) is current device
Scanning mmc 0:7...
[    4.278946] dwmmc_rockchip ff520000.dwmmc: IDMAC supports 32-bit address mode.
[    4.286163] dwmmc_rockchip ff520000.dwmmc: Using internal DMA controller.
[    4.293219] dwmmc_rockchip ff520000.dwmmc: Version ID is 270a
[    4.300124] dwmmc_rockchip ff520000.dwmmc: DW MMC controller at irq 42,32 bit host data width,256 deep fifo
[    4.321238] mmc_host mmc0: Bus speed (slot 0) = 400000Hz (slot req 400000Hz, actual 400000HZ div = 0)
[    4.342314] dwmmc_rockchip ff520000.dwmmc: 1 slots initialized
[    4.354638] dwmmc_rockchip ff500000.dwmmc: IDMAC supports 32-bit address mode.
[    4.366369] dwmmc_rockchip ff500000.dwmmc: Using internal DMA controller.
[    4.377939] dwmmc_rockchip ff500000.dwmmc: Version ID is 270a
[    4.389435] dwmmc_rockchip ff500000.dwmmc: DW MMC controller at irq 43,32 bit host data width,256 deep fifo
[    4.413245] mmc_host mmc1: Bus speed (slot 0) = 400000Hz (slot req 400000Hz, actual 400000HZ div = 0)
[    4.422362] mmc0: MAN_BKOPS_EN bit is not set
[    4.433031] mmc_host mmc0: Bus speed (slot 0) = 200000000Hz (slot req 200000000Hz, actual 200000000HZ div = 0)
[    4.440708] dwmmc_rockchip ff500000.dwmmc: 1 slots initialized
[    4.777281] dwmmc_rockchip ff520000.dwmmc: Successfully tuned phase to 130
[    4.788948] mmc0: new HS200 MMC card at address 0001
[    4.795315] mmcblk0: mmc0:0001 M8B16G 14.5 GiB
[    4.801400] mmcblk0boot0: mmc0:0001 M8B16G partition 1 4.00 MiB
[    4.807624] mmcblk0boot1: mmc0:0001 M8B16G partition 2 4.00 MiB
[    4.814001] mmcblk0rpmb: mmc0:0001 M8B16G partition 3 4.00 MiB
[    4.826491]  mmcblk0: p1 p2 p3 p4 p5 p6 p7
[    5.838858] EXT4-fs (mmcblk0p7): mounted filesystem with writeback data mode. Opts: (null)

Android 9.0
Code:
mmc2:cmd19,100
SdmmcInit=2 0
SdmmcInit=0 NOT PRESENT
[email protected]: 1, [email protected]: 0
mmc_init: -95, time 9
mmc0(part 0) is current device
[    0.962221] mmc1: MAN_BKOPS_EN bit is not set
[    0.966062] mmc_host mmc1: Bus speed (slot 0) = 150000000Hz (slot req 150000000Hz, actual 150000000HZ div = 0)
[    1.231560] dwmmc_rockchip ff520000.dwmmc: Successfully tuned phase to 59
[    1.231840] mmc1: new HS200 MMC card at address 0001
[    1.232850] mmcblk1: mmc1:0001 M8B16G 14.5 GiB
[    1.233344] mmcblk1boot0: mmc1:0001 M8B16G partition 1 4.00 MiB
[    1.233785] mmcblk1boot1: mmc1:0001 M8B16G partition 2 4.00 MiB
[    1.234247] mmcblk1rpmb: mmc1:0001 M8B16G partition 3 4.00 MiB
[    1.238752]  mmcblk1: p1 p2 p3 p4 p5 p6 p7 p8 p9 p10 p11 p12 p13 p14 p15 p16 p17 p18 p19 p20 p21


Arch

Code:
SdmmcInit=2 0
SdmmcInit=0 2
MMC:   [email protected]: 1, [email protected]: 0
Loading Environment from MMC... Card did not respond to voltage select!
mmc0(part 0) is current device
Scanning mmc 0:1...
[    2.308634] sdmmc-regulator GPIO handle specifies active low - ignored
[    5.361796] dwmmc_rockchip ff500000.dwmmc: IDMAC supports 32-bit address mode.
[    5.362451] dwmmc_rockchip ff500000.dwmmc: Using internal DMA controller.
[    5.363049] dwmmc_rockchip ff500000.dwmmc: Version ID is 270a
[    5.363582] dwmmc_rockchip ff500000.dwmmc: DW MMC controller at irq 30,32 bit host data width,256 deep fifo
[    5.375529] mmc_host mmc0: Bus speed (slot 0) = 400000Hz (slot req 400000Hz, actual 400000HZ div = 0)
[    5.389424] dwmmc_rockchip ff520000.dwmmc: IDMAC supports 32-bit address mode.
[    5.390073] dwmmc_rockchip ff520000.dwmmc: Using internal DMA controller.
[    5.390678] dwmmc_rockchip ff520000.dwmmc: Version ID is 270a
[    5.391227] dwmmc_rockchip ff520000.dwmmc: DW MMC controller at irq 31,32 bit host data width,256 deep fifo
[    5.392699] mmc_host mmc1: card is non-removable.
[    5.405616] mmc_host mmc1: Bus speed (slot 0) = 400000Hz (slot req 400000Hz, actual 400000HZ div = 0)
[    5.506161] mmc_host mmc1: Bus speed (slot 0) = 200000000Hz (slot req 200000000Hz, actual 200000000HZ div = 0)
[    5.519143] dwmmc_rockchip ff520000.dwmmc: All phases work, using default phase 0.
[    5.519977] mmc1: new HS200 MMC card at address 0001
[    5.521352] mmcblk1: mmc1:0001 M8B16G 14.5 GiB
[    5.522333] mmcblk1boot0: mmc1:0001 M8B16G partition 1 4.00 MiB
[    5.523436] mmcblk1boot1: mmc1:0001 M8B16G partition 2 4.00 MiB
[    5.524127] mmcblk1rpmb: mmc1:0001 M8B16G partition 3 4.00 MiB, chardev (235:0)
[    5.643216]  mmcblk1: p1 p2 p3
[    5.670155] dwmmc_rockchip ff520000.dwmmc: All phases work, using default phase 0.
[    5.683787] dwmmc_rockchip ff520000.dwmmc: All phases work, using default phase 0.
[    5.699757] mmc_host mmc1: Bus speed (slot 0) = 400000Hz (slot req 400000Hz, actual 400000HZ div = 0)
[    5.750133] mmc_host mmc1: Bus speed (slot 0) = 200000000Hz (slot req 200000000Hz, actual 200000000HZ div = 0)
[    5.764708] dwmmc_rockchip ff520000.dwmmc: All phases work, using default phase 0.
[    5.780067] dwmmc_rockchip ff520000.dwmmc: All phases work, using default phase 0.
[    5.780778] blk_update_request: I/O error, dev mmcblk1, sector 64 op 0x0:(READ) flags 0x80700 phys_seg 1 prio class 0
[    5.798095] dwmmc_rockchip ff520000.dwmmc: All phases work, using default phase 0.


It seems that problem is in phase selection (don't know what it means; could anyone explain, please?). Can this be fixed with some kernel parameters?
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#4
I've came across this thread https://forum.pine64.org/archive/index.p...-5258.html - which have helped: the max-frequency setting to the 150mhz in the dtb file makes ArchLinux boot.
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