The Ram Read / Wirte Speed ?
#1
HI , 

Have anyone to tried use A1 SD Bench tested speed ?

Thank !
If I am wrong please correct my content , thank !



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#2
Hi Joe, can you fix your thread title please? While I tested RAM using ssvb's tinymembench on Rock64 (4GB LPDDR3-1600), there are also some iozone results of an A1 Sandisk card in the SD-Card thread (https://forum.pine64.org/showthread.php?...8#pid28378).

Code:
==========================================================================
== Memory bandwidth tests                                               ==
==                                                                      ==
== Note 1: 1MB = 1000000 bytes                                          ==
== Note 2: Results for 'copy' tests show how many bytes can be          ==
==         copied per second (adding together read and writen           ==
==         bytes would have provided twice higher numbers)              ==
== Note 3: 2-pass copy means that we are using a small temporary buffer ==
==         to first fetch data into it, and only then write it to the   ==
==         destination (source -> L1 cache, L1 cache -> destination)    ==
== Note 4: If sample standard deviation exceeds 0.1%, it is shown in    ==
==         brackets                                                     ==
==========================================================================

C copy backwards                                     :   1433.8 MB/s (0.7%)
C copy backwards (32 byte blocks)                    :   1462.1 MB/s
C copy backwards (64 byte blocks)                    :   1359.9 MB/s (0.4%)
C copy                                               :   1371.3 MB/s (0.4%)
C copy prefetched (32 bytes step)                    :   1295.9 MB/s
C copy prefetched (64 bytes step)                    :   1461.6 MB/s (0.2%)
C 2-pass copy                                        :   1660.7 MB/s (0.1%)
C 2-pass copy prefetched (32 bytes step)             :   1223.4 MB/s
C 2-pass copy prefetched (64 bytes step)             :   1178.7 MB/s (0.1%)
C fill                                               :   5694.9 MB/s
C fill (shuffle within 16 byte blocks)               :   5694.3 MB/s
C fill (shuffle within 32 byte blocks)               :   5694.4 MB/s
C fill (shuffle within 64 byte blocks)               :   5696.0 MB/s
---
standard memcpy                                      :   1330.3 MB/s
standard memset                                      :   5696.0 MB/s
---
NEON LDP/STP copy                                    :   1532.2 MB/s
NEON LDP/STP copy pldl2strm (32 bytes step)          :   1272.3 MB/s (0.5%)
NEON LDP/STP copy pldl2strm (64 bytes step)          :   1476.1 MB/s
NEON LDP/STP copy pldl1keep (32 bytes step)          :   1677.4 MB/s
NEON LDP/STP copy pldl1keep (64 bytes step)          :   1679.9 MB/s
NEON LD1/ST1 copy                                    :   1515.7 MB/s (0.2%)
NEON STP fill                                        :   5696.7 MB/s
NEON STNP fill                                       :   2277.0 MB/s
ARM LDP/STP copy                                     :   1531.5 MB/s
ARM STP fill                                         :   5696.4 MB/s
ARM STNP fill                                        :   2336.4 MB/s (1.1%)

==========================================================================
== Framebuffer read tests.                                              ==
==                                                                      ==
== Many ARM devices use a part of the system memory as the framebuffer, ==
== typically mapped as uncached but with write-combining enabled.       ==
== Writes to such framebuffers are quite fast, but reads are much       ==
== slower and very sensitive to the alignment and the selection of      ==
== CPU instructions which are used for accessing memory.                ==
==                                                                      ==
== Many x86 systems allocate the framebuffer in the GPU memory,         ==
== accessible for the CPU via a relatively slow PCI-E bus. Moreover,    ==
== PCI-E is asymmetric and handles reads a lot worse than writes.       ==
==                                                                      ==
== If uncached framebuffer reads are reasonably fast (at least 100 MB/s ==
== or preferably >300 MB/s), then using the shadow framebuffer layer    ==
== is not necessary in Xorg DDX drivers, resulting in a nice overall    ==
== performance improvement. For example, the xf86-video-fbturbo DDX     ==
== uses this trick.                                                     ==
==========================================================================

NEON LDP/STP copy (from framebuffer)                 :    306.2 MB/s
NEON LDP/STP 2-pass copy (from framebuffer)          :    288.2 MB/s
NEON LD1/ST1 copy (from framebuffer)                 :     80.5 MB/s
NEON LD1/ST1 2-pass copy (from framebuffer)          :     79.4 MB/s
ARM LDP/STP copy (from framebuffer)                  :    157.8 MB/s
ARM LDP/STP 2-pass copy (from framebuffer)           :    152.9 MB/s

==========================================================================
== Memory latency test                                                  ==
==                                                                      ==
== Average time is measured for random memory accesses in the buffers   ==
== of different sizes. The larger is the buffer, the more significant   ==
== are relative contributions of TLB, L1/L2 cache misses and SDRAM      ==
== accesses. For extremely large buffer sizes we are expecting to see   ==
== page table walk with several requests to SDRAM for almost every      ==
== memory access (though 64MiB is not nearly large enough to experience ==
== this effect to its fullest).                                         ==
==                                                                      ==
== Note 1: All the numbers are representing extra time, which needs to  ==
==         be added to L1 cache latency. The cycle timings for L1 cache ==
==         latency can be usually found in the processor documentation. ==
== Note 2: Dual random read means that we are simultaneously performing ==
==         two independent memory accesses at a time. In the case if    ==
==         the memory subsystem can't handle multiple outstanding       ==
==         requests, dual random read has the same timings as two       ==
==         single reads performed one after another.                    ==
==========================================================================

block size : single random read / dual random read
     1024 :    0.0 ns          /     0.0 ns
     2048 :    0.0 ns          /     0.0 ns
     4096 :    0.0 ns          /     0.0 ns
     8192 :    0.0 ns          /     0.0 ns
    16384 :    0.0 ns          /     0.0 ns
    32768 :    0.1 ns          /     0.1 ns
    65536 :    5.3 ns          /     9.0 ns
   131072 :    8.1 ns          /    12.7 ns
   262144 :   11.3 ns          /    16.4 ns
   524288 :   66.5 ns          /   104.9 ns
  1048576 :  101.0 ns          /   142.5 ns
  2097152 :  119.3 ns          /   157.9 ns
  4194304 :  133.1 ns          /   169.8 ns
  8388608 :  141.1 ns          /   177.0 ns
 16777216 :  146.9 ns          /   182.6 ns
 33554432 :  150.9 ns          /   186.5 ns
 67108864 :  163.6 ns          /   207.0 ns
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