04-04-2022, 09:03 AM
I am trying some baremetal project.
And stuck with two problems:
1st RAMWR does not work for me in code below. ST7789V accepts the data, but ignores it: display stays black. I can't find why.
2nd might come from first problem. I use STLink V2 and flash like:
1st window:
openocd.exe -s ..\scripts\ -f interface\stlink.cfg -f target\nrf52.cfg -c "bindto 0.0.0.0"
2nd window:
arm-none-eabi-gdb --batch -ex="target extended-remote 127.0.0.1:3333" -ex "monitor program c:/pine/mbr.bin 0x00000000" -ex "monitor reset"
arm-none-eabi-gdb -ex="target extended-remote 127.0.0.1:3333"
and in gdb I need to issue "r" command to have any effect.
I.E. reboot after flash does not happen by itself, also after program exec instead of reboot I have HardFault.
Display is not dead: latest infinitime works for me on that device.
Any hints?
Compiled and gzipped code from the above:
And stuck with two problems:
1st RAMWR does not work for me in code below. ST7789V accepts the data, but ignores it: display stays black. I can't find why.
2nd might come from first problem. I use STLink V2 and flash like:
1st window:
openocd.exe -s ..\scripts\ -f interface\stlink.cfg -f target\nrf52.cfg -c "bindto 0.0.0.0"
2nd window:
arm-none-eabi-gdb --batch -ex="target extended-remote 127.0.0.1:3333" -ex "monitor program c:/pine/mbr.bin 0x00000000" -ex "monitor reset"
arm-none-eabi-gdb -ex="target extended-remote 127.0.0.1:3333"
and in gdb I need to issue "r" command to have any effect.
I.E. reboot after flash does not happen by itself, also after program exec instead of reboot I have HardFault.
Display is not dead: latest infinitime works for me on that device.
Any hints?
Code:
.syntax unified
.cpu cortex-m4
.arch armv7e-m
.thumb
.section .text,"ax"
.balign 4
.equ GPIO_BASE, 0x50000000
.equ GPIO_OUT, 0x504
.equ GPIO_OUTSET, 0x508
.equ GPIO_OUTCLR, 0x50C
.equ GPIO_IN, 0x510
.equ GPIO_DIR, 0x514
.equ GPIO_DIRSET, 0x518
.equ GPIO_DIRCLR, 0x51C
.equ FLASH_SELECT, 5
.equ LCD_SCK, 2
.equ LCD_MOSI, 3
.equ LCD_MISO, 4
.equ LCD_SELECT, 25
.equ LCD_COMMAND, 18
.equ LCD_RESET, 26
.equ LCD_BACKLIGHT_LOW, 14
.equ LCD_BACKLIGHT_MID, 22
.equ LCD_BACKLIGHT_HIGH, 23
.equ LCD_OUTPUTS_CONTROL_MASK, (1<<LCD_SCK) | (1<<LCD_MOSI) | (1<<LCD_SELECT) | (1<<LCD_COMMAND) | (1<<LCD_RESET)
.equ LCD_OUTPUTS_BACKLIGHT_MASK, (1<<LCD_BACKLIGHT_LOW) | (1<<LCD_BACKLIGHT_MID) | (1<<LCD_BACKLIGHT_HIGH)
.equ LCD_SPI_BASE, 0x40003000
.equ LCD_SPI_ENABLE, 0x500
.equ LCD_SPI_PSELSCK, 0x508
.equ LCD_SPI_PSELMOSI, 0x50C
.equ LCD_SPI_PSELMISO, 0x510
.equ LCD_SPI_RXD, 0x518
.equ LCD_SPI_TXD, 0x51C
.equ LCD_SPI_FREQUENCY, 0x524
.equ LCD_SPI_CONFIG, 0x554
.equ LCD_SPI_EVENTS_READY, 0x108
.equ LCD_WIDTH, 8
.equ LCD_HEIGHT, 8
.equ LCD_FULL_BYTES_SIZE, (LCD_WIDTH*LCD_HEIGHT)
.equ CMD_SWRESET, 0x01
.equ CMD_SLPOUT, 0x11
.equ CMD_COLMOD, 0x3A
.equ CMD_NORON, 0x13 // Normal Display Mode On
.equ CMD_INVOFF, 0x20 // Display Inversion Off
.equ CMD_INVON, 0x21 // Display Inversion On
.equ CMD_DISPOFF, 0x28 // Display Off
.equ CMD_DISPON, 0x29 // Display On
.equ CMD_CASET, 0x2A // Column Address Set
.equ CMD_RASET, 0x2B // Row Address Set
.equ CMD_RAMWR, 0x2C // Memory Write
.equ CMD_RAMRD, 0x2E // Memory Read
.equ CMD_MADCTL, 0x36 // Memory Data Access Control
.equ CMD_VSCSAD, 0x37 // Vertical Scroll Start Address of RAM
.equ CMD_RAMCTRL, 0xB0 // RAM Control
.equ CMD_PORCTRL, 0xB2 // Porch Setting
.equ CMD_CMD2EN, 0xDF // Command 2 Enable
.equ PUSH_BUTTON_IN, 13
.equ PUSH_BUTTON_OUT, 15
.equ GPIO_OUTPUTS_MASK, FLASH_SELECT | LCD_OUTPUTS_CONTROL_MASK | LCD_OUTPUTS_BACKLIGHT_MASK
.equ GPIO_INPUTS_MASK, (1<<LCD_MISO)
.macro Sleep Reg, Tacts
MOV \Reg, \Tacts
loop\@:
SUBS \Reg, 1
BNE loop\@
.endm
__Vectors:
.org 0
.word __initial_sp // Top of Stack
.word Reset_Handler // Reset Handler
.word NMI_Handler // NMI Handler
.word HardFault_Handler // Hard Fault Handler
.word MemManage_Handler // MPU Fault Handler
.word BusFault_Handler // Bus Fault Handler
.word UsageFault_Handler // Usage Fault Handler
.word 0 // 7 Reserved
.word 0 // 8 Reserved
.word 0 // 9 Reserved
.word 0 // 10 Reserved
.word SVCall_Handler // Supervisor Call Handler
.word DebugMonitor_Handler // Debug Monitor Handler
.word 0 // 13 Reserved
.word PendSV_Handler // Deferred Supervisor Call Handler
.word SysTick_Handler // System Timer Handler
.word CLOCK_POWER_BPROT_Handler // 00 Clock control / Power control / Block Protect
.word RADIO_Handler // 01 2.4 GHz radio
.word UARTE0_Handler // 02 Universal Asynchronous Receiver/Transmitter with EasyDMA
.word SPIM0_SPIS0_TWIM0_TWIS0_Handler // 03 SPI master 0 / SPI slave 0 / Two-wire interface master 0 / Two-wire interface slave 0
.word SPIM1_SPIS1_TWIM1_TWIS1_Handler // 04 SPI master 1 / SPI slave 1 / Two-wire interface master 1 / Two-wire interface slave 1
.word NFCT_Handler // 05 Near Field Communication Tag
.word GPIOTE_Handler // 06 GPIO Tasks and Events
.word SAADC_Handler // 07 Analog to digital converter
.word TIMER0_Handler // 08 Timer 0
.word TIMER1_Handler // 09 Timer 1
.word TIMER2_Handler // 0A Timer 2
.word RTC0_Handler // 0B Real-time counter 0
.word TEMP_Handler // 0C Temperature sensor
.word RNG_Handler // 0D Random number generator
.word ECB_AES_Handler // 0E Electronic Code Book (ECB) mode block encryption
.word CCM_AAR_Handler // 0F AES CCM Mode Encryption / Acelerated Address Resolver
.word WDT_Handler // 10 Watchdog timer
.word RTC1_Handler // 11 Real-time counter 1
.word QDEC_Handler // 12 Quadrature decoder
.word LPCOMP_Handler // 13 Low power comparator
.word COMP_Handler // 14 General purpose comparator
.word EGU0_SWI0_Handler // 15 Event Generator Unit 0 / Software interrupt 0
.word EGU1_SWI1_Handler // 16 Event Generator Unit 1 / Software interrupt 1
.word EGU2_SWI2_Handler // 17 Event Generator Unit 2 / Software interrupt 2
.word EGU3_SWI3_Handler // 18 Event Generator Unit 3 / Software interrupt 3
.word EGU4_SWI4_Handler // 19 Event Generator Unit 4 / Software interrupt 4
.word EGU5_SWI5_Handler // 1A Event Generator Unit 5 / Software interrupt 5
.word TIMER3_Handler // 1B Timer 3
.word TIMER4_Handler // 1C Timer 4
.word PWM0_Handler // 1D Pulse Width Modulation Unit 0
.word PDM_Handler // 1E Pulse Density Modulation (Digital Microphone Interface)
.word NVMC_Handler // 1F Non-Volatile Memory Controller
.word PPI_Handler // 20 Programmable Peripheral Interconnect
.word MWU_Handler // 21 Memory Watch Unit
.word PWM1_Handler // 22 Pulse Width Modulation Unit 1
.word PWM2_Handler // 23 Pulse Width Modulation Unit 2
.word SPIS2_Handler // 24 SPI slave 2
.word SPIM2_Handler // 25 SPI master 2
.word RTC2_Handler // 26 Real-time counter 2
.word I2S_Handler // 27 Inter-IC Sound Interface
.word FPU_Handler // 28 FPU interrupt
.word ISR_29_Handler // 29 ISR_Handler
.word ISR_2A_Handler // 2A ISR_Handler
.word ISR_2B_Handler // 2B ISR_Handler
.word ISR_2C_Handler // 2C ISR_Handler
.word ISR_2D_Handler // 2D ISR_Handler
.word ISR_2E_Handler // 2E ISR_Handler
.word ISR_2F_Handler // 2F ISR_Handler
NMI_Handler: // NMI Handler
B Reset
HardFault_Handler: // Hard Fault Handler
B Reset
MemManage_Handler: // MPU Fault Handler
B Reset
BusFault_Handler: // Bus Fault Handler
B Reset
UsageFault_Handler: // Usage Fault Handler
B Reset
SVCall_Handler: // Supervisor call Handler
B Reset
DebugMonitor_Handler: // Debug Monitor Handler
B Reset
PendSV_Handler: // Deferred Supervisor Call Handler
B Reset
SysTick_Handler: // System Timer Handler
B Reset
CLOCK_POWER_BPROT_Handler: // 00 Clock control / Power control / Block Protect
B Reset
RADIO_Handler: // 01 2.4 GHz radio
B Reset
UARTE0_Handler: // 02 Universal Asynchronous Receiver/Transmitter with EasyDMA
B Reset
SPIM0_SPIS0_TWIM0_TWIS0_Handler: // 03 SPI master 0 / SPI slave 0 / Two-wire interface master 0 / Two-wire interface slave 0
B .
SPIM1_SPIS1_TWIM1_TWIS1_Handler: // 04 SPI master 1 / SPI slave 1 / Two-wire interface master 1 / Two-wire interface slave 1
B .
NFCT_Handler: // 05 Near Field Communication Tag
B .
GPIOTE_Handler: // 06 GPIO Tasks and Events
B .
SAADC_Handler: // 07 Analog to digital converter
B .
TIMER0_Handler: // 08 Timer 0
B .
TIMER1_Handler: // 09 Timer 1
B .
TIMER2_Handler: // 0A Timer 2
B .
RTC0_Handler: // 0B Real-time counter 0
B .
TEMP_Handler: // 0C Temperature sensor
B .
RNG_Handler: // 0D Random number generator
B .
ECB_AES_Handler: // 0E Electronic Code Book (ECB) mode block encryption
B .
CCM_AAR_Handler: // 0F AES CCM Mode Encryption / Acelerated Address Resolver
B .
WDT_Handler: // 10 Watchdog timer
B .
RTC1_Handler: // 11 Real-time counter 1
B .
QDEC_Handler: // 12 Quadrature decoder
B .
LPCOMP_Handler: // 13 Low power comparator
B .
COMP_Handler: // 14 General purpose comparator
B .
EGU0_SWI0_Handler: // 15 Event Generator Unit 0 / Software interrupt 0
B .
EGU1_SWI1_Handler: // 16 Event Generator Unit 1 / Software interrupt 1
B .
EGU2_SWI2_Handler: // 17 Event Generator Unit 2 / Software interrupt 2
B .
EGU3_SWI3_Handler: // 18 Event Generator Unit 3 / Software interrupt 3
B .
EGU4_SWI4_Handler: // 19 Event Generator Unit 4 / Software interrupt 4
B .
EGU5_SWI5_Handler: // 1A Event Generator Unit 5 / Software interrupt 5
B .
TIMER3_Handler: // 1B Timer 3
B .
TIMER4_Handler: // 1C Timer 4
B .
PWM0_Handler: // 1D Pulse Width Modulation Unit 0
B .
PDM_Handler: // 1E Pulse Density Modulation (Digital Microphone Interface)
B .
NVMC_Handler: // 1F Non-Volatile Memory Controller
B .
PPI_Handler: // 20 Programmable Peripheral Interconnect
B .
MWU_Handler: // 21 Memory Watch Unit
B .
PWM1_Handler: // 22 Pulse Width Modulation Unit 1
B .
PWM2_Handler: // 23 Pulse Width Modulation Unit 2
B .
SPIS2_Handler: // 24 SPI slave 2
B .
SPIM2_Handler: // 25 SPI master 2
B .
RTC2_Handler: // 26 Real-time counter 2
B .
I2S_Handler: // 27 Inter-IC Sound Interface
B .
FPU_Handler: // 28 FPU interrupt
B .
ISR_29_Handler: // 29 ISR Handler
B .
ISR_2A_Handler: // 2A ISR Handler
B .
ISR_2B_Handler: // 2B ISR Handler
B .
ISR_2C_Handler: // 2C ISR Handler
B .
ISR_2D_Handler: // 2D ISR Handler
B .
ISR_2E_Handler: // 2E ISR Handler
B .
ISR_2F_Handler: // 2F ISR Handler
B .
Reset_Handler:
lcd_init:
MOV R7, GPIO_BASE
LDR R6, =LCD_SPI_BASE
LDR R0, =GPIO_OUTPUTS_MASK
STR R0, [R7, GPIO_DIRSET]
LDR R0, =GPIO_INPUTS_MASK
STR R0, [R7, GPIO_DIRCLR]
MOV R0, (1<<FLASH_SELECT) // Deactivate FlashMemory
STR R0, [R7, GPIO_OUTSET]
MOV R0, (1<<LCD_SELECT) // Activate Display
STR R0, [R7, GPIO_OUTCLR]
MOV R0, (1<<LCD_COMMAND)
STR R0, [R7, GPIO_OUTSET]
MOV R0, (1<<LCD_RESET)
STR R0, [R7, GPIO_OUTSET]
LDR R0, =LCD_OUTPUTS_BACKLIGHT_MASK
STR R0, [R7, GPIO_OUTSET]
MOV R0, (1<<LCD_BACKLIGHT_HIGH)
STR R0, [R7, GPIO_OUTCLR]
MOV R0, 0
STR R0, [R6, LCD_SPI_ENABLE]
MOV R0, 0
STR R0, [R6, LCD_SPI_EVENTS_READY]
MOV R0, LCD_SCK
STR R0, [R6, LCD_SPI_PSELSCK]
MOV R0, LCD_MOSI
STR R0, [R6, LCD_SPI_PSELMOSI]
MOV R0, LCD_MISO
STR R0, [R6, LCD_SPI_PSELMISO]
MOV R0, 0x80000000 // 8Mbps
STR R0, [R6, LCD_SPI_FREQUENCY]
MOV R0, (1<<2) | (1<<1) // CPOL=ActiveLow | CPHA=Trailing | ORDER=MsbFirst
STR R0, [R6, LCD_SPI_CONFIG]
//MOV R0, 1
//STR R0, [R6, LCD_SPI_ENABLE]
MOV R0, (1<<LCD_RESET)
STR R0, [R7, GPIO_OUTCLR]
Sleep R1, 0x1000000
STR R0, [R7, GPIO_OUTSET]
Sleep R1, 0x1000000
MOV R0, CMD_SWRESET
BL lcd_transfer_cmd
Sleep R0, 0x1000000
MOV R0, CMD_SLPOUT
BL lcd_transfer_cmd
Sleep R0, 0x100000
MOV R0, CMD_VSCSAD
BL lcd_transfer_cmd
MOV R0, 0x00
BL lcd_transfer_data
BL lcd_transfer_data
Sleep R0, 0x10000
// MOV R0, CMD_CMD2EN
// BL lcd_transfer_cmd
// MOV R0, 0x5A
// BL lcd_transfer_data
// MOV R0, 0x69
// BL lcd_transfer_data
// MOV R0, 0x02
// BL lcd_transfer_data
// MOV R0, 0x01
// BL lcd_transfer_data
// Sleep R0, 0x10000
//
// MOV R0, CMD_RAMCTRL
// BL lcd_transfer_cmd
// MOV R0, 0x00
// BL lcd_transfer_data
// MOV R0, 0xF0
// BL lcd_transfer_data
// Sleep R0, 0x10000
//
// MOV R0, CMD_PORCTRL
// BL lcd_transfer_cmd
// MOV R0, 0x0C
// BL lcd_transfer_data
// BL lcd_transfer_data
// MOV R0, 0x00
// BL lcd_transfer_data
// MOV R0, 0x33
// BL lcd_transfer_data
// BL lcd_transfer_data
// Sleep R0, 0x10000
//
// MOV R0, CMD_CMD2EN
// BL lcd_transfer_cmd
// MOV R0, 0x5A
// BL lcd_transfer_data
// MOV R0, 0x69
// BL lcd_transfer_data
// MOV R0, 0x02
// BL lcd_transfer_data
// MOV R0, 0x00
// BL lcd_transfer_data
// Sleep R0, 0x10000
MOV R0, CMD_COLMOD
BL lcd_transfer_cmd
MOV R0, 0x66 // 888
BL lcd_transfer_data
Sleep R0, 0x100
MOV R0, CMD_MADCTL
BL lcd_transfer_cmd
MOV R0, 0x00
BL lcd_transfer_data
Sleep R0, 0x100
fill_display:
MOV R0, CMD_CASET
BL lcd_transfer_cmd
MOV R0, 0
BL lcd_transfer_data
BL lcd_transfer_data
BL lcd_transfer_data
MOV R0, LCD_WIDTH
BL lcd_transfer_data
MOV R0, CMD_RASET
BL lcd_transfer_cmd
MOV R0, 0
BL lcd_transfer_data
BL lcd_transfer_data
BL lcd_transfer_data
MOV R0, LCD_HEIGHT
BL lcd_transfer_data
MOV R0, CMD_RAMWR
BL lcd_transfer_cmd
MOV R3, 0xFFFFFFFF
fill_display_data1:
LDR R2, =LCD_FULL_BYTES_SIZE
fill_display_data:
MOV R0, R3
BL lcd_transfer_data
MOV R0, 0
BL lcd_transfer_data
BL lcd_transfer_data
SUBS R2, 1
BNE fill_display_data
Sleep R0, 0x100000
MOV R0, CMD_DISPOFF
BL lcd_transfer_cmd
Sleep R0, 0x100000
MOV R0, CMD_DISPON
BL lcd_transfer_cmd
Sleep R0, 0x100000
//MOV R0, (1<<LCD_SELECT) // Deactivate Display
//STR R0, [R7, GPIO_OUTSET]
LDR R0, =LCD_OUTPUTS_BACKLIGHT_MASK
STR R0, [R7, GPIO_OUTSET]
Sleep R0, 0x100000
MOV R0, (1<<LCD_BACKLIGHT_HIGH)
STR R0, [R7, GPIO_OUTCLR]
Sleep R0, 0x100000
//MOV R0, (1<<LCD_SELECT) // Activate Display
//STR R0, [R7, GPIO_OUTCLR]
MOV R0, CMD_INVON
BL lcd_transfer_cmd
MOV R0, CMD_NORON
BL lcd_transfer_cmd
LSRS R3, R3, 1
BNE fill_display_data1
LDR R0, =LCD_OUTPUTS_BACKLIGHT_MASK
STR R0, [R7, GPIO_OUTSET]
B Reset
lcd_transfer_cmd:
MOV R1, (1<<LCD_SELECT) // Activate Display
STR R1, [R7, GPIO_OUTCLR]
MOV R1, (1<<LCD_COMMAND)
STR R1, [R7, GPIO_OUTCLR]
B lcd_transfer
lcd_transfer_data:
MOV R1, (1<<LCD_SELECT) // Activate Display
STR R1, [R7, GPIO_OUTCLR]
MOV R1, (1<<LCD_COMMAND)
STR R1, [R7, GPIO_OUTSET]
B lcd_transfer // Hang if removed: display needs time to sense command/data line
lcd_transfer: // R6, R7, R0, R1
MOV R1, 1
STR R1, [R6, LCD_SPI_ENABLE]
MOV R1, 0
STR R1, [R6, LCD_SPI_EVENTS_READY]
STR R0, [R6, LCD_SPI_TXD]
lcd_transfer1:
LDR R1, [R6, LCD_SPI_EVENTS_READY]
ORRS R1, R1
BNE lcd_transfer1
LDR R1, [R6, LCD_SPI_RXD]
MOV R1, 0
STR R1, [R6, LCD_SPI_ENABLE]
MOV R1, (1<<LCD_SELECT) // Activate Display
STR R1, [R7, GPIO_OUTSET]
BX LR
Reset:
MOV R0, 0xE000E000 // #define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */
ADD R0, 0x0D00 // #define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */
ADD R0, 0x00C // __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */
LDR R1, [R0]
MOV R2, 0xFFFF
AND R1, R2
MOV R2, 0x05FA
LSL R2, R2, 16
ORR R1, R2
ORR R1, (1<<2) // #define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */
STR R1, [R0]
B .
.equ nextboot, 0x1000
.equ versionsize, 32
.equ __initial_sp, 0x20010000 // Top of Stack
.equ __initial_sp2_ptr, nextboot // Top of Stack of next boot loader
.poolCompiled and gzipped code from the above:
Code:
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