07-23-2021, 05:41 PM
Some debugging later I've figured out why reset wasn't working: I built my u-boot in such a way that it contained SCP coprocessor firmware. Apparently that firmware can cause that a reboot of Linux doesn't trigger the reset line at all.
Building u-boot without the SCP firmware solves the problem.
I've put instructions on building u-boot for the SoPine (including a version for in the SPI flash chip and flashing instructions) here: https://github.com/renzenicolai/uboot-pi...tructions/
My next goal is going to be submitting the clusterboard devicetree and configuration file to upstream u-boot, let's see how that goes
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Another note: instead of doing the diode modification the reset problem can also be fixed by removing the resistors between the inverters (U54/U55) and the reset lines of the SoPine modules. By doing that you effectively disable the reset circuit (causing the reset button to do nothing at all), but in return the boards will always reset correctly and you solve the design mistake (the inverter drives directly against the SoC itself, which tries to pull the reset line low for rebooting but can't as the inverter keeps the line high). The resistors are in a row between the chips and the SoPine modules.
Building u-boot without the SCP firmware solves the problem.
I've put instructions on building u-boot for the SoPine (including a version for in the SPI flash chip and flashing instructions) here: https://github.com/renzenicolai/uboot-pi...tructions/
My next goal is going to be submitting the clusterboard devicetree and configuration file to upstream u-boot, let's see how that goes
.Another note: instead of doing the diode modification the reset problem can also be fixed by removing the resistors between the inverters (U54/U55) and the reset lines of the SoPine modules. By doing that you effectively disable the reset circuit (causing the reset button to do nothing at all), but in return the boards will always reset correctly and you solve the design mistake (the inverter drives directly against the SoC itself, which tries to pull the reset line low for rebooting but can't as the inverter keeps the line high). The resistors are in a row between the chips and the SoPine modules.