01-02-2018, 05:40 PM
Hi folks,
I'm somewhat confused by the SPI interfaces in the RK3328 and thus their application in the ROCK64.
I've dug through all the documentation. It appears that there are three SPI interfaces in the RK3328, per Pg. 483 of the technical reference manual.
In ROCK64_Schematic_v2.0_20171019.pdf and the ROCK64 Pi2 Bus diagram....
Pi2 Bus Pin 24 is marked as "SPI_CSN0_M2", Pin 26 is marked as "SPI_CSN1_M0"
This is the first thing that confused me. Why do we have only one CS belonging to two different SPI interfaces on the header ?
The SPI2 (m2) Interface is exposed on the header. It has only on CS, and can only have one device on the bus.
It appears that bus m2 is the same one used for the ROCK64 on-board 128M flash chip (U1) per page 6 of the schematics.
Question 1: If so, how does one use the SPI interface on the Pi-2 bus without also addressing the onboard 128M Flash ?
Question 2: What was the purpose of exposing SPI_CSN1_M0 to the header when the rest of SPI_M0 is inaccessible ?
As far as I can tell, interface M0 and M1 are not used. In fact, it may even be that these interfaces aren't available on the BGA - I can't find them on the Ball Map.
I am wondering if future versions of the ROCK64 will make any changes? If so, is there a forum or suitable place to send suggestions ?
Suggestion: If possible, populate the header with a usable SPI bus e.g. m0 or m1, and provide both cs lines, e.g.
Pin 19: SPI_TXD_Mx
Pin 21: SPI_RXD_Mx
Pin 23: SPI_CLK_Mx
Pin 24: SPI_CSN0_Mx
Pin 26: SPI_CSN1_Mx
Cheers.
I'm somewhat confused by the SPI interfaces in the RK3328 and thus their application in the ROCK64.
I've dug through all the documentation. It appears that there are three SPI interfaces in the RK3328, per Pg. 483 of the technical reference manual.
Code:
INTERFACE CLOCK RXD TXD CSN0 CSN1
SPI0 (m0) clkm0 : GPIO2B0 rxdm0 : GPIO2B2 txdm0 : GPIO2B1 csn0m0 : GPIO2B3 csn1m0 : GPIO2B4
SPI1 (m1) clkm1 : GPIO3C7 rxdm1 : GPIO3D0 txdm1 : GPIO3D1 csn0m1 : GPIO3D2 csn1m1 : GPIO3D3
SPI2 (m2) clkm2 : GPIO3A0 rxdm2 : GPIO3A2 txdm2 : GPIO3A1 csn0m2 : GPIO3B0 N/AIn ROCK64_Schematic_v2.0_20171019.pdf and the ROCK64 Pi2 Bus diagram....
Pi2 Bus Pin 24 is marked as "SPI_CSN0_M2", Pin 26 is marked as "SPI_CSN1_M0"
This is the first thing that confused me. Why do we have only one CS belonging to two different SPI interfaces on the header ?
The SPI2 (m2) Interface is exposed on the header. It has only on CS, and can only have one device on the bus.
It appears that bus m2 is the same one used for the ROCK64 on-board 128M flash chip (U1) per page 6 of the schematics.
Question 1: If so, how does one use the SPI interface on the Pi-2 bus without also addressing the onboard 128M Flash ?
Question 2: What was the purpose of exposing SPI_CSN1_M0 to the header when the rest of SPI_M0 is inaccessible ?
As far as I can tell, interface M0 and M1 are not used. In fact, it may even be that these interfaces aren't available on the BGA - I can't find them on the Ball Map.
I am wondering if future versions of the ROCK64 will make any changes? If so, is there a forum or suitable place to send suggestions ?
Suggestion: If possible, populate the header with a usable SPI bus e.g. m0 or m1, and provide both cs lines, e.g.
Pin 19: SPI_TXD_Mx
Pin 21: SPI_RXD_Mx
Pin 23: SPI_CLK_Mx
Pin 24: SPI_CSN0_Mx
Pin 26: SPI_CSN1_Mx
Cheers.