How many SPI ports/buses are broken out/available on SOQUARTZ?

[gogerriko]

I plan on writing some example overlays myself for SPI stuff on soquartz over at https://github.com/CounterPillow/overlay-examples soon, I just haven't gotten around to it yet.

Yes, that would be really helpful. 

UPDATE:
I thought I understood what to do based on the Radxa overlays (see below for original reply) but your pointer to look at the rk356x.dtsi now has me a little unsure that I have done this correctly.

Extracting the snippet for SPI3 shows that both CS0 and CS1 are already defined in the dtsi, so do then I assume that once the status for SPI3 changes from disabled to okay, both CS0 and CS1 pins are treated by the CPU as handling chip select functions. As in, I cannot use the CS1 pin for something else if SPI3 is enabled.

I also don't have to create two "spidevs" for each cs# pin etc.

Code:

spi3: spi@fe640000 {
  compatible = "rockchip,rk3568-spi", "rockchip,rk3066-spi";
  reg = <0x0 0xfe640000 0x0 0x1000>;
  interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>;
  clocks = <&cru CLK_SPI3>, <&cru PCLK_SPI3>;
  clock-names = "spiclk", "apb_pclk";
  dmas = <&dmac0 26>, <&dmac0 27>;
  dma-names = "tx", "rx";
  pinctrl-names = "default";
  pinctrl-0 = <&spi3m0_cs0 &spi3m0_cs1 &spi3m0_pins>;
  #address-cells = <1>;
  #size-cells = <0>;
  status = "disabled";
};

ORIGINAL REPLY:

I have got it setup using cs0 (i.e. using just a single cs). I've also created a script to bind the spidev to spi3.0 at boot up.

Code:

/dts-v1/;
/plugin/;

/ {
        fragment@0 {
                target = <&spi3>;

                __overlay__ {
                        status = "okay";
                        #address-cells = <1>;
                        #size-cells = <0>;

                        spidev@0 {
                                compatible = "spidev";
                                status = "okay";
                                reg = <0>;
                        }; 
                };
        };         
};