how to use spidev0.1?

[monte]

Hello,

I want to use spi0.1 on rock64 (ver 3.0).
I tried enabling rockchip-spi-spidev in armbian-config, but it didn't work. When I open the dtb, it seems that it is not for rk3328 as there is "compatible = "rockchip,rk3399"".
Where can I find the right dts?

I tired:

add num-cs into the rk3328-rock64.dts

Code:

        spi@ff190000 {
                compatible = "rockchip,rk3328-spi\0rockchip,rk3066-spi";
                reg = <0x00 0xff190000 0x00 0x1000>;
                interrupts = <0x00 0x31 0x04>;
                #address-cells = <0x01>;
                #size-cells = <0x00>;
                clocks = <0x02 0x20 0x02 0xd1>;
                clock-names = "spiclk\0apb_pclk";
                dmas = <0x12 0x08 0x12 0x09>;
                dma-names = "tx\0rx";
                pinctrl-names = "default";
                pinctrl-0 = <0x32 0x33 0x34 0x35 0xb6>;
                status = "okay";
                phandle = <0x86>;
                num-cs = <2>;

                spiflash@0 {
                        compatible = "jedec,spi-nor";
                        reg = <0x00>;
                        spi-max-frequency = <0x2faf080>;
                };
        };

dmesg:
[    3.239265] rockchip-spi ff190000.spi: Failed to register controller
[    3.239495] rockchip-spi: probe of ff190000.spi failed with error -22

You need to declare cs-gpios option like this:

Code:

spi@ff190000 {
                compatible = "rockchip,rk3328-spi\0rockchip,rk3066-spi";
                reg = <0x00 0xff190000 0x00 0x1000>;
                interrupts = <0x00 0x31 0x04>;
                #address-cells = <0x01>;
                #size-cells = <0x00>;
                clocks = <0x02 0x20 0x02 0xd1>;
                clock-names = "spiclk\0apb_pclk";
                dmas = <0x12 0x08 0x12 0x09>;
                dma-names = "tx\0rx";
                pinctrl-names = "default";
                pinctrl-0 = <0x32 0x33 0x34 0x35>;
                cs-gpios = <0x81 0x07 0x62>;
                status = "okay";
                phandle = <0x81>;

                spidev@0 {
                        compatible = "rockchip,spidev";
                        reg = <0x01>;
                        spi-max-frequency = <0x186a0>;                     
                };
        };

This will use GPIO3_A7 as CS1 and it will appear at /dev/spidev0.1
The problem is SPI is still unusable for my needs, because it keeps CLK idle HIGH and MOSI idle LOW for some unknown reason, and I wasn't able to change this behavior with any manipulations with driver or device tree.