[Article] Star64 JH7110 + NuttX RTOS: RISC-V Privilege Levels and UART Registers - Printable Version +- PINE64 (https://forum.pine64.org) +-- Forum: General (https://forum.pine64.org/forumdisplay.php?fid=1) +--- Forum: General (https://forum.pine64.org/forumdisplay.php?fid=74) +--- Thread: [Article] Star64 JH7110 + NuttX RTOS: RISC-V Privilege Levels and UART Registers (/showthread.php?tid=18526)

[Article] Star64 JH7110 + NuttX RTOS: RISC-V Privilege Levels and UART Registers - lupyuen - 07-18-2023 We’re in the super-early stage of porting Apache NuttX Real-Time Operating System (RTOS) to the Star64 64-bit RISC-V SBC. (Based on StarFive JH7110 SoC) In this article we’ll talk about the interesting things that we learnt about RISC-V and Star64 JH7110… (1) What are RISC-V Privilege Levels     (And why they make NuttX a little more complicated) (2) What is NuttX Kernel Mode     (And how it differs from Flat Mode) (3) All about JH7110’s UART Registers     (And how they are different from other 16550 UARTs) (4) Why (naively) porting NuttX from QEMU to Star64 might become really challenging!     (Thankfully we have the LiteX Arty-A7 and PolarFire Icicle ports) https://lupyuen.codeberg.page/articles/privilege.html