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+--- Thread: Segfault with GCC in Armbian [Solved]. (/showthread.php?tid=11209)
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RE: Segfault with GCC in Armbian [Solved]. - ejolson - 09-05-2020
To continue this story of over and under clocking memory for stability. Here is a graph showing the relative memory bandwidth of the Rock64 with different memory clock speeds.
![[Image: rock64_400.svg]](http://fractal.math.unr.edu/~ejolson/pi/stream/rock64_400.svg)
Again both of the Rock64 single-board computers I have seem stable with the memory clock set to 400 MHz. Since the errors at 786 MHz are intermittent, my guess is the memory could still go a little faster, perhaps 600 MHz or even 666 MHz.
Does anyone know how to make uboot files which initialize the memory at 600 or 666 MHz?
RE: Segfault with GCC in Armbian [Solved]. - tomarm - 10-04-2020
I don't. But I do thank you ejolson for delving into this issue some of us have. Our boards should have been replaced free imo but this thread may offer us hope in getting ours /mine to compile pkgs properly. Some care about other uses like a smooth desktop, games, video and this would help them too. I'll test whatever you get done just leave us instruction steps please.
RE: Segfault with GCC in Armbian [Solved]. - hexdump - 01-17-2021
i have just successfully created my own custom ddr.bin with 666mhz mem freq following the idea from here:
https://forum.libreelec.tv/thread/10140-latest-libreelec-for-rockchip-rk3229/?postID=132388#post132388
by simply changing the freq values in the ddr.bin with a hex editor - in my case i used it for a rk3328 tv box,
but i think it will work the same way for the rock64 too ... here are my notes about it:
https://github.com/hexdump0815/u-boot-misc/blob/master/misc.rk3328/rk3328_ddr_333MHz_v1.15-666mhz.readme
good luck and best wishes - hexdump
RE: Segfault with GCC in Armbian [Solved]. - stelabentley - 07-07-2021
This is a followup post to to confirm that the Rock64 board that was experiencing segmentation faults with the default 786 MHz memory clock on Armbian is now stable with the uboot-initialized 333 MHz setting.
On a selection of computational benchmarks performance is about 77 percent of the original setting;
for compilations with gcc more than 80 percent of the original performance is retained with the added advantage that the system doesn't crash and the compiler doesn't create segmentation faults.
I understand, but did not verify, that setting the memory clocks to 333 MHz has a noticeable affect on video playback.
As far as I'm concerned this problem is solved and I'll try to mark it as such. Although one out of the two Rock64 single-board computers I have required this configuration change, based on posts appearing on this forum, my suspicion is a much less than 50 percent--perhaps closer to 10 or 20 percent--of systems in use actually exhibit this problem.
Even so, I would favor a note on the wiki support page for the Rock64 explaining how to work around system instability by reducing the DDR RAM memory clock.
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