Full Version: Reading ADI pixel port, 8 pins at 27 MHz, with DMA – possible?
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Analog Devices has this legacy NTSC/PAL decoder ADV7280. It's nice because it has only 32 pins. Output are 8 pins called "pixel port", which is clocked depending on input – for NTSC it's 27 MHz (similar or the same for PAL).

The 27 MHz clock is exposed at LLC pin. The pixel port bytes at ticks of the clock are: Cb,Y,Cr,Y,Cb,Y,Cr,Y, etc. – Y (luma) for each pixel, only one of Cb / Cr for each pixel (chroma subsampling) – 16 bits per pixel.

I need to read whole frame (but there is interlacing – half of lines! and I only need that), for PAL it will be: 2 * 576 / 2 * 720 = 414.72 kB (16 bits per pixel, half of 576i lines, 720 pixels per line). This should fit into Padi Stamp memory? I'm worried that the memory is divided to some sort of sections (as it is in case of stm32f07, that's why I'm considering Padi Stamp).

I saw DMA behaves well: – looks like DMA operates at half of main 83 MHz clock – great result! I need to read 27 MHz port, and: 83 MHz / 3 = 27,667 – so I need one third of the main clock – spare cycles, apparently! I'm only worried that my DMA will be reading pins and writing memory (so it's opposite), and that in general my DMA use will be different, so things may go bad.

For STM32 I would use a timer-counter peripheral on source side of DMA, set to be externally clocked by the video decoder (LLC pin), to generate a DMA event every N clock edges (I plan to skip some pixels, but in general this can be at each of 27 MHz clock edge – no pixel skip) – then read the 8 bit pixel port and store it to RAM (so memory is on destination side of DMA). When the frame is complete, I will drive 32x16 RGB LED matrix (so much pixels skipped – that's the plan).

Is this project possible? Is there any show stopper maybe? Will the DMA be able to read the pixel port?

Best regards,
I think, it would be too much for Padi Stamp/ RTL8710AF.

415kB of RAM for the video, plus some input buffer, plus the output buffer for for 32x16 RGB - No chance

GPIO DMA 8 pin/bits video + clock (LLC pin) + HS interrupt pin + VS interrupt pin.

I don't think the chip even supports externally clocked input GPIO DMA.

Might be able to use SDIOD (Devide) peripheral - it has got 4 bits, and takes external CLK