PINE64

Full Version: Bit-banding
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Bit banding (feature of Cortex M3) works well, as expected.

.66MHz CPU

gpio_write 1, and then gpio_write 0 takes ~0.57us
gpio_write(&gpio_ledC3, 1);
gpio_write(&gpio_ledC3, 0);

Bit-Banding =1, and then Bit-Banding = 0 takes ~0.17 us
GPIO_C3 = 1;
GPIO_C3 = 0;

#define BITBAND_PERI_REF   0x40000000
#define BITBAND_PERI_BASE  0x42000000
#define BITBAND_PERI(a,b) ((BITBAND_PERI_BASE + (a-BITBAND_PERI_REF)*32 + (b*4)))  // Convert PERI address

#define P0_ADDR 0x40001000
#define GPIO_A0 *((volatile unsigned char *)(BITBAND_PERI(GPIO_REG_BASE,0))) //Port = 0, bit = 0, A0
#define GPIO_A1 *((volatile unsigned char *)(BITBAND_PERI(GPIO_REG_BASE,1))) //Port = 0, bit = 1, A1
#define GPIO_A2 *((volatile unsigned char *)(BITBAND_PERI(GPIO_REG_BASE+12,0))) //Port = 1, bit = 0, A2
#define GPIO_A3 *((volatile unsigned char *)(BITBAND_PERI(GPIO_REG_BASE+12,1))) //Port = 1, bit = 1, A3
#define GPIO_A4 *((volatile unsigned char *)(BITBAND_PERI(GPIO_REG_BASE+12,2))) //Port = 1, bit = 2, A4
#define GPIO_A5 *((volatile unsigned char *)(BITBAND_PERI(GPIO_REG_BASE+12,3))) //Port = 1, bit = 3, A5

#define GPIO_C0 *((volatile unsigned char *)(BITBAND_PERI(GPIO_REG_BASE+12,10))) //Port = 1, bit = 10, C0
#define GPIO_C1 *((volatile unsigned char *)(BITBAND_PERI(GPIO_REG_BASE,6))) //Port = 0, bit = 6, C1
#define GPIO_C2 *((volatile unsigned char *)(BITBAND_PERI(GPIO_REG_BASE+12,11))) //Port = 1, bit = 11, C2
#define GPIO_C3 *((volatile unsigned char *)(BITBAND_PERI(GPIO_REG_BASE,7))) //Port = 0, bit = 7, C3
#define GPIO_C4 *((volatile unsigned char *)(BITBAND_PERI(GPIO_REG_BASE,8))) //Port = 0, bit = 8, C4
#define GPIO_C5 *((volatile unsigned char *)(BITBAND_PERI(GPIO_REG_BASE,9))) //Port = 0, bit = 9, C5

other port addresses:
PA_0 pin_name: 0, port_num: 0, pin_num: 0, addr_shiftDDR: 4, DR:0, chip_pin: 0
PA_1 pin_name: 1, port_num: 0, pin_num: 1, addr_shiftDDR: 4, DR:0, chip_pin: 1
PA_2 pin_name: 32, port_num: 1, pin_num: 0, addr_shiftDDR: 16, DR:12, chip_pin: 2
PA_3 pin_name: 33, port_num: 1, pin_num: 1, addr_shiftDDR: 16, DR:12, chip_pin: 3
PA_4 pin_name: 34, port_num: 1, pin_num: 2, addr_shiftDDR: 16, DR:12, chip_pin: 4
PA_5 pin_name: 35, port_num: 1, pin_num: 3, addr_shiftDDR: 16, DR:12, chip_pin: 5
PB_0 pin_name: 38, port_num: 1, pin_num: 6, addr_shiftDDR: 16, DR:12, chip_pin: 16
PB_1 pin_name: 39, port_num: 1, pin_num: 7, addr_shiftDDR: 16, DR:12, chip_pin: 17
PB_2 pin_name: 40, port_num: 1, pin_num: 8, addr_shiftDDR: 16, DR:12, chip_pin: 18
PB_3 pin_name: 2, port_num: 0, pin_num: 2, addr_shiftDDR: 4, DR:0, chip_pin: 19
PB_4 pin_name: 3, port_num: 0, pin_num: 3, addr_shiftDDR: 4, DR:0, chip_pin: 20
PB_5 pin_name: 41, port_num: 1, pin_num: 9, addr_shiftDDR: 16, DR:12, chip_pin: 21
PC_0 pin_name: 42, port_num: 1, pin_num: 10, addr_shiftDDR: 16, DR:12, chip_pin: 32
PC_1 pin_name: 6, port_num: 0, pin_num: 6, addr_shiftDDR: 4, DR:0, chip_pin: 33
PC_2 pin_name: 43, port_num: 1, pin_num: 11, addr_shiftDDR: 16, DR:12, chip_pin: 34
PC_3 pin_name: 7, port_num: 0, pin_num: 7, addr_shiftDDR: 4, DR:0, chip_pin: 35
PC_4 pin_name: 8, port_num: 0, pin_num: 8, addr_shiftDDR: 4, DR:0, chip_pin: 36
PC_5 pin_name: 9, port_num: 0, pin_num: 9, addr_shiftDDR: 4, DR:0, chip_pin: 37
PE_0 pin_name: 47, port_num: 1, pin_num: 15, addr_shiftDDR: 16, DR:12, chip_pin: 64
PE_1 pin_name: 21, port_num: 0, pin_num: 21, addr_shiftDDR: 4, DR:0, chip_pin: 65
PE_2 pin_name: 22, port_num: 0, pin_num: 22, addr_shiftDDR: 4, DR:0, chip_pin: 66
PE_3 pin_name: 23, port_num: 0, pin_num: 23, addr_shiftDDR: 4, DR:0, chip_pin: 67
PE_4 pin_name: 48, port_num: 1, pin_num: 16, addr_shiftDDR: 16, DR:12, chip_pin: 68
PE_5 pin_name: 24, port_num: 0, pin_num: 24, addr_shiftDDR: 4, DR:0, chip_pin: 69

[attachment=661]
[attachment=660]