40 pin header

I assume this is up-to-date: ROCK64_Schematic_v2.0_20170704.pdf

Is it true that the following "dedicated signals" could be re-purposed as regular IO as they only go the 40-pin header?


Also, why does SPI_CSN0_M2 appear on this header? It is dedicated as a chip select on SPI flash IC U1 (the GD25Q128CS).

Any use of this pin as either SPI or GPIO will cause U1 to drive the MISO pin (pin 21 on the 40 pin header).

Also, the graphic that shows the 40-pin header (ROCK64_Pi-2 _and_Pi_P5+_Bus.pdf) states the the SDMMC0_xxxx pins can be used as GPIO as long as no MicroSD is used.

How do these pins operate during boot? If they are intended to be used as GPIO by an application, the boot process may inadvertently cause a daughterboard to react because the application hasn't booted yet.

Any guidance would be appreciated.

Messages In This Thread
40 pin header - by GaryLa - 01-03-2018, 11:15 AM
RE: 40 pin header - by GaryLa - 01-05-2018, 09:52 AM
RE: 40 pin header - by zehks - 01-05-2018, 07:37 PM
RE: 40 pin header - by GaryLa - 01-06-2018, 01:11 PM
RE: 40 pin header - by xalius - 01-07-2018, 06:57 AM
RE: 40 pin header - by GaryLa - 01-07-2018, 11:58 AM

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