/dev/spidev0,0 on the Rock64 - Does anyone know how to enable it?

[mcerveny]

SPI with user programs (python) for Rock64:

1. There is only one SPI on rk3328 device with possible 2 chipselects CSN0/CSN1.
   
2. Rockchip chose "pin multiplex 2 for SPI" (check pins *_M2 and spi2_* + grf_con_spi_io_sel in TRM) as default. This is wrong choice because only one chipselect (CSN0) is available on pin (GPIO3_B0 (SPI_CSN0_M2)).
   
3. Chipselect CSN0 is used in Rock64 to activate embedded SPI-NOR flash (GD25Q128) and therefore unavailable to user (I requested RFE to be optional). Internal BOOTROM can boot only from SPI-NOR/CSN0. SPI is already enabled "okay" in DTS but only with embedded SPI-NOR flash.
   
4. Let's enable SPI for user (need set driver "rockchip,spidev") with non-wired CSN1 (dynamically without reboot on ayufan kernel with backported configfs).
   
   Code:

   # cat >spi1.dts <<EOF
/dts-v1/;
/plugin/;

/ {
        compatible = "pine64,rock64";

        fragment@0 {
                target-path = "/spi@ff190000";
                __overlay__ {
                        spidev@1 {
                                compatible="rockchip,spidev";
                                reg=<1>;
                                spi-max-frequency=<10000000>;
                        };
                };
        };
};
EOF
# dtc spi1.dts -o spi1.dtbo
# mkdir /sys/kernel/config/device-tree/overlays/spi1
# cat spi1.dtbo > /sys/kernel/config/device-tree/overlays/spi1/dtbo
# ls /dev/spidev*
/dev/spidev32766.1
5. Connect SPI device:
   • pin 19 (GPIO3_A1 (SPI_TXD_M2)) -> device SI
     
   • pin 21 (GPIO3_A2 (SPI_RXD_M2)) <- device SO (not used in e-paper device)
     
   • pin 24 (GPIO3_A0 (SPI_CLK_M2)) -> device CLK (There is bug in v2.0 hardware that swapped pins 23/24!)
     
   • any other pin (for example 26) -> device CS
     
6. Let's try SPI with python and AT45DB041D SPI-NOR flash . Because CSN1 is unavailable program must simulate CSN1 before any access of SPI transfer functions.
   
   Code:

   # apt install python-pip python-setuptools python-dev
# pip install spidev
# git clone https://github.com/Leapo/Rock64-R64.GPIO.git
# ln -s Rock64-R64.GPIO/R64 .
# ./spi.py
JEDEC: 1f 24 00 00 00 00

run with parameters 'sector' or 'erase' or 'compare file' or 'write file'
# ./spi.py erase
JEDEC: 1f 24 00 00 00 00

chip erase ...
wait  wait  wait  wait  wait  wait  wait  wait  wait  wait  wait  wait  wait  wait  wait  ...  done

# ./spi.py write file
: 1f 24 00 00 00 00

write ...

00000000 size 100: d0 0d fe ed  ...  wait  wait  wait  wait  wait  wait  
00000100 size 100: 00 00 00 4c  ...  wait  wait  wait  wait  wait  wait  
00000200 size 100: 00 00 01 38  ...  wait  wait  wait  wait  wait  wait  
...
# ./spi.py compare file
JEDEC: 1f 24 00 00 00 00

compare ...

Demo code is attached. Happy hacking and buy me a Beer.