RFE for next ROCK64

[mcerveny]

The SPI pins should be reworked:

• Embedded SPI-NOR flash (GD25Q128) should stay on SPI "pin multiplex 2" to be boot compatible with u-boot DTS and bootable from internal BOOTROM without modification and NOT connected to pinheader. This is usable for booting and upgrading SPI-NOR flash from u-boot (and after multiplexer switch from linux). "pinheader/switch" from previous post to suppress CSN0 to embedded SPI-NOR flash is not needed.
  • CLK == spi2_clk == GPIO3_A0 == spi0m2_clk
    
  • MISO == spi2_rxd == GPIO3_A2 == spi0m2_rx
    
  • MOSI == spi2_txd == GPIO3_A1 == spi0m2_tx
    
  • CS == spi2_csn0 == GPIO3_B0 == spi0m2_cs0
    
• SPI "pin multiplex 0" will be used in linux and connected to pinheader. This will also change linux DTS for Rock64 (rk3328-rock64.dts) (and probably routing data to switch multiplex back to zero must be added (check GRF_COM_IOMUX/grf_con_spi_io_sel in TRM)):
  
  Code:

  &spi0 {
    status = "okay";
    pinctrl-0 = <&spi0m0_clk &spi0m0_tx &spi0m0_rx &spi0m0_cs0 &spi0m0_cs1>;
    spidev@0 {
        compatible="rockchip,spidev";
        reg=<0>;
        spi-max-frequency=<50000000>;
    };
    spidev@1 {
        compatible="rockchip,spidev";
        reg=<1>;
        spi-max-frequency=<50000000>;
    };
};
  • CLK == spi0_clk == GPIO2_B0 == spi0m0_clk == pin 23
    
  • MOSI == spi0_txd == GPIO2_B2 == spi0m0_tx == pin 19
    
  • MISO == spi0_rxd == GPIO2_B1 == spi0m0_rx == pin 21
    
  • CS0 == spi0_csn0 == GPIO2_B3 == spi0m0_cs0 == pin 24
    
  • CS1 == spi0_csn1 == GPIO2_B4 == spi0m0_cs1 == pin 26 (already routed)
    

Impossible. There are none of SPI multiplex 0 (GPIO2_B0-3) pins outside RK3328 chip with cheap BGA395 package !