Are you sure the codec GPIO isn't an output?
It's too late in my day for me to recall which channel is which on a TRRS jack, but you're probably right.
J2 is drawn funny. Are 4&6 and 5&3 shorted?? If so, how can the left channel work at all? If not, something is missing to make insertion detection work.
I *thought* that I verified that mine has discreet left and right channels at that jack. But it's been a while so I may be wrong.
If 4 and 6 are actually a switch, then we're back to a conventional design, the codec GPIO doesn't necessarily have to be an output, and L and R can be separate. But then how can insertion detection be a logic level??
It's too late in my day for me to recall which channel is which on a TRRS jack, but you're probably right.
J2 is drawn funny. Are 4&6 and 5&3 shorted?? If so, how can the left channel work at all? If not, something is missing to make insertion detection work.
I *thought* that I verified that mine has discreet left and right channels at that jack. But it's been a while so I may be wrong.
If 4 and 6 are actually a switch, then we're back to a conventional design, the codec GPIO doesn't necessarily have to be an output, and L and R can be separate. But then how can insertion detection be a logic level??