DDR Version 1.15 20181010 In soft reset SRX Channel 0: LPDDR4,50MHz CS = 0 MR0=0x98 MR4=0x1 MR5=0xFF MR8=0x8 MR12=0x4D MR14=0x4D MR18=0x0 MR19=0x0 MR24=0x8 MR25=0x0 CS = 1 MR0=0x18 MR4=0x1 MR5=0xFF MR8=0x8 MR12=0x4D MR14=0x4D MR18=0x0 MR19=0x0 MR24=0x8 MR25=0x0 Bus Width=32 Col=10 Bank=8 Row=15/15 CS=2 Die Bus-Width=16 Size=2048MB Channel 1: LPDDR4,50MHz CS = 0 MR0=0x98 MR4=0x1 MR5=0xFF MR8=0x8 MR12=0x4D MR14=0x4D MR18=0x0 MR19=0x0 MR24=0x8 MR25=0x0 CS = 1 MR0=0x18 MR4=0x1 MR5=0xFF MR8=0x8 MR12=0x4D MR14=0x4D MR18=0x0 MR19=0x0 MR24=0x8 MR25=0x0 Bus Width=32 Col=10 Bank=8 Row=15/15 CS=2 Die Bus-Width=16 Size=2048MB 256B stride channel 0 CS = 0 MR0=0x98 MR4=0x1 MR5=0xFF MR8=0x8 MR12=0x72 MR14=0x72 MR18=0x0 MR19=0x0 MR24=0x8 MR25=0x0 CS = 1 MR0=0x18 MR4=0x1 MR5=0xFF MR8=0x8 MR12=0x72 MR14=0x72 MR18=0x0 MR19=0x0 MR24=0x8 MR25=0x0 channel 1 CS = 0 MR0=0x98 MR4=0x1 MR5=0xFF MR8=0x8 MR12=0x72 MR14=0x72 MR18=0x0 MR19=0x0 MR24=0x8 MR25=0x0 CS = 1 MR0=0x18 MR4=0x1 MR5=0xFF MR8=0x8 MR12=0x72 MR14=0x72 MR18=0x0 MR19=0x0 MR24=0x8 MR25=0x0 channel 0 training pass! channel 1 training pass! change freq to 400MHz 0,1 channel 0 CS = 0 MR0=0x98 MR4=0x1 MR5=0xFF MR8=0x8 MR12=0x72 MR14=0x72 MR18=0x0 MR19=0x0 MR24=0x8 MR25=0x0 CS = 1 MR0=0x18 MR4=0x1 MR5=0xFF MR8=0x8 MR12=0x72 MR14=0x72 MR18=0x0 MR19=0x0 MR24=0x8 MR25=0x0 channel 1 CS = 0 MR0=0x98 MR4=0x1 MR5=0xFF MR8=0x8 MR12=0x72 MR14=0x72 MR18=0x0 MR19=0x0 MR24=0x8 MR25=0x0 CS = 1 MR0=0x18 MR4=0x1 MR5=0xFF MR8=0x8 MR12=0x72 MR14=0x72 MR18=0x0 MR19=0x0 MR24=0x8 MR25=0x0 channel 0 training pass! channel 1 training pass! change freq to 800MHz 1,0 ch 0 ddrconfig = 0x101, ddrsize = 0x2020 ch 1 ddrconfig = 0x101, ddrsize = 0x2020 pmugrf_os_reg[2] = 0x3AA1FAA1, stride = 0xD OUT Boot1: 2017-06-09, version: 1.09 CPUId = 0x0 ChipType = 0x10, 1896 SdmmcInit=2 0 BootCapSize=100000 UserCapSize=119276MB FwPartOffset=2000 , 100000 SdmmcInit=0 0 BootCapSize=0 UserCapSize=60350MB FwPartOffset=2000 , 0 StorageInit ok = 75722 LoadTrustBL No find bl30.bin No find bl32.bin Load uboot, ReadLba = 2000 Load OK, addr=0x200000, size=0xdd03c RunBL31 0x10000 NOTICE: BL31: v1.3(debug):22b599a NOTICE: BL31: Built : 11:03:32, Jul 10 2019 NOTICE: BL31: Rockchip release version: v1.1 INFO: GICv3 with legacy support detected. ARM GICV3 driver initialized in EL3 INFO: Using opteed sec cpu_context! INFO: boot cpu mask: 0 INFO: plat_rockchip_pmu_init(1181): pd status 3e INFO: BL31: Initializing runtime services WARNING: No OPTEE provided by BL2 boot loader, Booting device without OPTEE initialization. SMC`s desK ERROR: Error initializing runtime service opteed_fast INFO: BL31: Preparing for EL3 exit to normal world INFO: Entry point address = 0x200000 INFO: SPSR = 0x3c9 fdtdec_get_addr_size_fixed: reg: addr=ff770000, size=10000 fdtdec_get_addr_size_fixed: reg: addr=ff320000, size=1000 U-Boot 2017.09-03642-g183e247 (Nov 21 2019 - 20:31:11 -0500) Model: Pine64 RK3399 Pinebook Pro DRAM: 3.9 GiB Sysmem: init Relocation Offset is: f5bf0000 I2c0 speed: 400000Hz PMIC: RK808 vdd_center 900000 uV vdd_log init 900000 uV rk_board_init PWM2 pinctrl init fail! rk_board_init: vcc3v0_sdio cannot set regulator value -38 vdd_center 900000 uV DCDC_REG1@ vdd_center: 750000uV <-> 1400000uV, set 900000uV, enabling | suspendd DCDC_REG4@ vcc_1v8: 1800000uV <-> 1800000uV, set 1800000uV, enabling | suspendg LDO_REG1@ vcc1v8_dvp: 1800000uV <-> 1800000uV, set 1800000uV, enabling | suspendg LDO_REG4@ vcc_sd: 3300000uV <-> 3300000uV, set 3300000uV, enabling | suspendg LDO_REG7@ vcca1v8_codec: 1800000uV <-> 1800000uV, set 1800000uV, enabling | suspendg LDO_REG8@ vcc_3v0: 3000000uV <-> 3000000uV, set 3000000uV, enabling | suspendg SWITCH_REG2@ vcc3v3_s0: -61uV <-> -61uV, set 0uV, enabling | suspendd dc-12v@ dc_12v: 12000000uV <-> 12000000uV, set 12000000uV, enabling | susp) vcc-sys@ vcc_sys: 5000000uV <-> 5000000uV, set 5000000uV, enabling | suspend) vcc3v3-sys@ vcc3v3_sys: 3300000uV <-> 3300000uV, set 3300000uV, enabling | suspend) vcc-phy-regulator@ vcc_phy: -61uV <-> -61uV, set -61uV, enabling | suspendg led-regulator@ led_regulator: -61uV <-> -61uV, set -61uV, enabling | suspendg vcc5v0-host-en@ vcc5v0_host: 5000000uV <-> 5000000uV, set 5000000uV, enabling | suspend) vcc5v0-usb3-host-regulator@vcc5v0_usb3_host: -61uV <-> -61uV, set -61uV, enabling | suspeg vcc5v0-typec0-en@ vcc5v0_typec0: -61uV <-> -61uV, set -61uV, enabling | suspendg vcc1v8-sdio@ vcc1v8_sdio: 1800000uV <-> 1800000uV, set 1800000uV, enabling | suspend) vcc3v0-sdio@ vcc3v0_sdio: 3000000uV <-> 3000000uV, set 3000000uV, enabling | suspend) vdd_log init 900000 uV vdd_log@ vdd_log: 800000uV <-> 1400000uV, set 900000uV, enabling | suspendV MMC: dwmmc@fe310000: 2, sdhci@fe330000: 0, dwmmc@fe320000: 1 Invalid bus 0 (err=-19) *** Warning - spi_flash_probe_bus_cs() failed, using default environment In: serial Out: serial Err: serial Model: Pine64 RK3399 Pinebook Pro syntax error Bootdev: mmc 0 PartType: RKPARM boot mode: None Load FDT from resource part Rockchip UBOOT DRM driver version: v1.0.1 "Synchronous Abort" handler, esr 0x96000010 * Relocate offset = 00000000f5bf0000 * ELR(PC) = 00000000002478c8 * LR = 00000000002478ac * SP = 00000000f3ddaf70 * ESR_EL2 = 0000000096000010 EC[31:26] == 100101, Exception from a Data abort, from current exception level IL[25] == 1, 32-bit instruction trapped * DAIF = 00000000000003c0 D[9] == 1, DBG masked A[8] == 1, ABORT masked I[7] == 1, IRQ masked F[6] == 1, FIQ masked * SPSR_EL2 = 0000000020000349 D[9] == 1, DBG masked A[8] == 1, ABORT masked I[7] == 0, IRQ not masked F[6] == 1, FIQ masked M[4] == 0, Exception taken from AArch64 M[3:0] == 1001, EL2h * SCTLR_EL2 = 0000000030c51835 I[12] == 1, Icaches enabled C[2] == 1, Dcache enabled M[0] == 1, MMU enabled * HCR_EL2 = 000000000800003a * VBAR_EL2 = 00000000f5df0800 * TTBR0_EL2 = 00000000f7ff0000 x0 : 0000000000000000 x1 : 000000000000000f x2 : 000000000000000a x3 : 00000000ff1a0000 x4 : 00000000ffffffff x5 : 0000000000000000 x6 : 0000000000000000 x7 : 00000000f5ea4ed8 x8 : 00000000f3ddb040 x9 : 0000000000000008 x10: 00000000ffffffd0 x11: 00000000f3e1e828 x12: 0000000000000000 x13: 0000000000000200 x14: 000000000000003a x15: 00000000ffffffff x16: 000000006077dc3e x17: 00000000845020ee x18: 00000000f3de7d10 x19: 00000000f3e109f0 x20: 00000000f5ea8788 x21: 00000000f3e10bd0 x22: 00000000f5e7b158 x23: 0000000000000000 x24: 0000000000000000 x25: 00000000f3e10c68 x26: 0000000000000000 x27: 0000000000000000 x28: 0000000000000000 x29: 00000000f3ddb150 SP: f3ddaf70: 00000000 00000000 00000000 00000000 f3ddaf80: 00000000 00000000 f5e97aae 00000000 f3ddaf90: 00000000 00000000 00000000 00000000 f3ddafa0: f5e97af5 00000000 f5e97b1b 00000000 f3ddafb0: f5e97b68 00000000 f5e97bb5 00000000 f3ddafc0: f5e97bf5 00000000 f5e97c35 00000000 f3ddafd0: f5e97c72 00000000 00000000 00000000 f3ddafe0: 00000000 00000000 f5e97caf 00000000 f3ddaff0: f3ddb150 00000000 f5df0a0c 00000000 f3ddb000: f3e109f0 00000000 f5ea8788 00000000 f3ddb010: f7ff0000 00000000 0800003a 00000000 f3ddb020: 30c51835 00000000 f3ddaf70 00000000 f3ddb030: 20000349 00000000 f5df0800 00000000 f3ddb040: 000003c0 00000000 96000010 00000000 f3ddb050: f5e378c8 00000000 00000000 00000000 f3ddb060: 0000000f 00000000 0000000a 00000000 Call trace: PC: [< 002478c8 >] LR: [< 002478ac >] Stack: [< 002478c8 >] [< 0023edd8 >] [< 0023f258 >] [< 0023f960 >] [< 00202e2c >] [< 00277c18 >] [< 0021a38c >] [< 0020199c >] Copy above stack info to a file(eg. dump.txt), and execute command in your U-Boot project: ./scripts/stacktrace.sh dump.txt Resetting CPU ...