Hi,
From the reference manual "Rockchip RK3399 TRM V1.3 Part2", Table 7-6 shows the MIPI DPHY PLL Settings for 27 MHz reference Clock. However, the default clock is 24 MHz (pll_refclk) for the RK3399.
How is the table generated for 24 MHz?
Thanks.
It seems you have never calculated PLLs modes. Usually it is quite straightforward.
Try the spreadsheet (OpenOffice Calc) in archive attached. I've created it by the data of the document you've mentioned in the message above. Fiddle the digits in green cells and look the result.
Only one unknown thing from "Rockchip RK3399 TRM V1.3 Part2" document is frequency range of "fbclk" frequency. I do not know how high it can be. Sure it can't be lower than 5MHz because of "Flexible input clock reference" requirement which is starting from 5MHz. With lowest available n=0 (N=1) divider value value the "fbclk" will be 5MHz too. So this value can be assumed as absolute minimum for "fbclk". The highest value is not disclosed in this document. From "Table 7-6" it is known to be not less than 27MHz.
Try to choose the values which are producing the closest to desired output frequency wile not violating the limits. Other values, icpctrl, lpfctrl and vcorange should correspond to Table 5-7.
Disclaimer: I have none RK3399 yet and had programmed only the PLLs of microcontrollers and PLLs on PC motherboards only.