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Full Version: PADI - Overclocking to 166MHz works well
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1/ By default PADI boots as 83.3MHz.

It can be switched to 166.6MHz, without any problems.

HalCpuClkConfig(CPU_CLOCK_SEL_VALUE); // 0 - 166666666 Hz, 1 - 83333333 Hz, 2 - 41666666 Hz, 3 - 20833333 Hz, 4 - 10416666 Hz, 5 - 4000000 Hz
HAL_LOG_UART_ADAPTER pUartAdapter;
pUartAdapter.BaudRate = RUART_BAUD_RATE_38400;
HalLogUartSetBaudRate(&pUartAdapter);

https://goo.gl/photos/uchA6XRzBJEoxk2w9

2/
At CPU speed 166MHz maximum CLK frequency on SSI peripheral is 20.8MHz

SSI CLK:
https://goo.gl/photos/uJJLC94C2G4A5ycA7
(11-02-2016, 08:52 PM)kissste Wrote: [ -> ]1/ By default PADI boots as 83.3MHz.

It can be switched to 166.6MHz, without any problems.

HalCpuClkConfig(CPU_CLOCK_SEL_VALUE); // 0 - 166666666 Hz, 1 - 83333333 Hz, 2 - 41666666 Hz, 3 - 20833333 Hz, 4 - 10416666 Hz, 5 - 4000000 Hz
HAL_LOG_UART_ADAPTER pUartAdapter;
pUartAdapter.BaudRate = RUART_BAUD_RATE_38400;
HalLogUartSetBaudRate(&pUartAdapter);

https://goo.gl/photos/uchA6XRzBJEoxk2w9

2/
At CPU speed 166MHz maximum CLK frequency on SSI peripheral is 20.8MHz

SSI CLK:
https://goo.gl/photos/uJJLC94C2G4A5ycA7

Awesome, great finding but not surprise Smile
RTL8710 running does 41MHz clock SPI on SPI1 peripheral

// SPI1 (S1)

#define SPI1_MOSI  PA_1
#define SPI1_MISO  PA_0
#define SPI1_SCLK  PA_2
#define SPI1_CS    PA_4


#define SCLK_FREQ 10416666*4 // 41.66MHz [email protected] ssi_idx=1 A-port

static void master_tr_done_callback(void *pdata, SpiIrq event)
{
   BaseType_t task_woken, result;
   ws2812_t *cfg;

   task_woken = pdFALSE;
   cfg = (ws2812_t *) pdata;

   switch (event) {
   case SpiRxIrq:
       break;
   case SpiTxIrq:
spi_master_write_stream_dma(&cfg->spi_master,
                               &(cfg->dma_buff[0]),
                               cfg->buff_len);
       break;
   default:
       DBG_8195A("unknown interrupt event!\n");
   }
}

As long as the DMA is re-fed rightaway on the interrupt, the stream is has got no delays/interruptions.

https://goo.gl/photos/K4riMupWi7GDKzLA8

Had to hack SDK a bit - disable FunctionChk in hal_ssi.c
for some reason it does not like B-port assignment and SPI1

   ret = FunctionChk(Function, (u32)PinmuxSelect);
   if(ret == _FALSE){
       DBG_SSI_ERR("Invalid Pinmux Setting.\n");
DBG_SSI_ERR("skipping...\n");
       //return HAL_ERR_PARA;
   }
(11-07-2016, 08:15 PM)kissste Wrote: [ -> ]RTL8710 running does 41MHz clock SPI on SPI1 peripheral

// SPI1 (S1)
#define SPI1_MOSI  PB_6
#define SPI1_MISO  PB_7
#define SPI1_SCLK  PB_5
#define SPI1_CS    PB_4

#define SCLK_FREQ 10416666*4 // 41.66MHz [email protected] ssi_idx=1 B-port
[...]
These GPIOs are not available on the board's pads. Did you connect directly to the chip's leads or is the SDK simply ignoring the pin mux and routes the signals to PA_x instead?
Tido
(11-08-2016, 04:37 AM)tidklaas Wrote: [ -> ]These GPIOs are not available on the board's pads. Did you connect directly to the chip's leads or is the SDK simply ignoring the pin mux and routes the signals to PA_x instead?
Tido

These 40MHz signals are on PA_ "A" ports

correct definitions (original post had "B" ports), which I re-defined to "A " ports as follows:
#define SPI1_MOSI  PA_1
#define SPI1_MISO  PA_0
#define SPI1_SCLK  PA_2
#define SPI1_CS    PA_4