11-28-2021, 08:48 PM
I'm working on SMBIOS support for the Quartz64, and the CPU reports that it supports the Arm64SocID SMC call.
But it's returning invalid values:
Jep106 code: 0xFFFFFAE0
SoC revision: 0xFFFFFB18
According to the SMC Calling Convention, the top bit of both should be zero:
SoC_ID_type == 0
JEP-106 code for the SiP
Bit[31] must be zero
Bits [30:24] JEP-106 bank index for
the SiP (see [9.])7
Bits [23:16] JEP-106 identification
code with parity bit for the SiP (see
[9.])7
Bits [15:0] Implementation defined
SoC ID
Bit[31] must be zero
Bits [30:0] SoC revision
How would I go about reporting this problem to Rockchip? I don't know if this is a problem they can fix in their rkbin repo, or if it's a hardware bug.
But it's returning invalid values:
Jep106 code: 0xFFFFFAE0
SoC revision: 0xFFFFFB18
According to the SMC Calling Convention, the top bit of both should be zero:
SoC_ID_type == 0
JEP-106 code for the SiP
Bit[31] must be zero
Bits [30:24] JEP-106 bank index for
the SiP (see [9.])7
Bits [23:16] JEP-106 identification
code with parity bit for the SiP (see
[9.])7
Bits [15:0] Implementation defined
SoC ID
Bit[31] must be zero
Bits [30:0] SoC revision
How would I go about reporting this problem to Rockchip? I don't know if this is a problem they can fix in their rkbin repo, or if it's a hardware bug.